control-flow operations

Concept

In the VAMP microprocessor case study, control-flow operations are a class of assembly-level instructions tested separately from memory, arithmetic, and logic operations. The VAMPasm instruction set contains 6 control operations, and the study treats branching operations with unit and sequence tests using predicates such as `is_branch`; examples include `IJ` and `IJALR` instruction sequences.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 4 chunks

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control-flow operations

Definition in the VAMP case study

The provided evidence identifies control-flow related operations as one of four instruction categories studied in model-based conformance testing of the VAMP processor, alongside memory-related load/store operations, arithmetic operations, and logic operations.[C1] At the VAMP assembly level, the VAMPasm instruction set contains 56 instructions, including 6 instructions for control operations.[C2]

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Instruction Set Architecture part of → 100% 2e

Control-flow operations are part of the VAMP instruction set.

LINKED ENTITIES

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HOL-TestGen used_for_testing The evidence presents HOL-TestGen as the framework used to generate unit and sequence test cases for instruction categories including control-flow related operations.

CITATIONS

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[1] Control-flow related operations are one of four instruction categories studied, alongside memory-related load/store, arithmetic, and logic operations. Test Program Generation for a Microprocessor: A Case Study

[2] VAMPasm contains 56 instructions, including 6 control operations. Test Program Generation for a Microprocessor: A Case Study

[3] The study tests control-flow related operations as branching operations using `is_branch`, with unit and sequence specifications and examples including `Ijalr`, `Ij`, and `IJALR`. Test Program Generation for a Microprocessor: A Case Study

[4] The VAMP ISA configuration includes `pcp`, the address of the next instruction to be executed, and `dcp`, the delayed program counter for the currently executed instruction; this mechanism is called delayed pc. Test Program Generation for a Microprocessor: A Case Study

[5] In the assembler-model configuration, `pcp` and `dcp` are represented as natural numbers for the program counter and delayed program counter. Test Program Generation for a Microprocessor: A Case Study

[6] The VAMP implements the full DLX instruction set, including jump-and-link operations. Test Program Generation for a Microprocessor: A Case Study

[7] The assembler model is used for black-box test generation to check that the processor behaves as described, independently of internal details such as interrupts, virtual memory, caching, pipelining, and instruction reordering. Test Program Generation for a Microprocessor: A Case Study

[8] Test-data generation in the considered scenarios is performed by constraint solving and random instantiation, and additional constraints can improve coverage by dividing the uniformity domain into interesting sub-domains. Test Program Generation for a Microprocessor: A Case Study