C++ Instruction Set Simulator

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The C++ Instruction Set Simulator is an automatically generated instruction set simulator produced from a complete formal property suite. The described approach translates an architectural ITL specification into a C++ simulation core, applies code-generation optimizations, and yields simulators whose measured performance is comparable to commercial just-in-time compiled simulator tooling while retaining equivalence to the verified design by construction.

First seen 5/26/2026

Last seen 5/26/2026

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Overview

The C++ Instruction Set Simulator is a generated instruction set simulator (ISS) whose source is derived from a complete, architectural-style property suite rather than from a manually reimplemented ISA model. In the described method, a formally verified property suite becomes a functionally equivalent architectural model of the verified processor design; the generated ISS is therefore equivalent to the design by construction after successful verification. [C1]

ISSs are used in processor and system design flows for pre-silicon software development, allowing software to be simulated before the target system is manufactured or even fully finished. The motivation for generating the C++ ISS is to avoid slow gate-level or cycle-accurate execution for software workloads while also avoiding a separate manual reimplementation of the ISA. [C2]

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Generating an Efficient Instruction Set Simulator from a Complete Property Suite ← introduces 100% 2e

The paper introduces an approach to generate a C++ instruction set simulator from a complete property suite.

Complete Property Suite uses → 100% 2e

The complete property suite is the source from which the C++ ISS is automatically generated.

Instruction Set Architecture implements → 100% 2e

The generated C++ ISS implements the instruction set architecture captured in the complete property suite.

Complete Property Suite derived from → 100% 2e

The C++ ISS is automatically generated from the complete property suite.

Instruction Cache uses → 90% 2e

The generated C++ ISS employs caching of decoded instructions similar to JIT-CS to improve performance.

Just-in-Time Compiled Simulation compares with → 100% 2e

The generated C++ ISS performance is benchmarked against JIT-CS commercial tools.

Interpretive Simulation compares with → 100% 1e

The generated C++ ISS clearly outperforms interpretive simulation.

CITATIONS

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[1] A complete formally verified property suite can serve as an architectural model, and a generated C++ ISS is equivalent to the verified design by construction. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[2] ISSs are important for pre-silicon software development and are used instead of gate-level or cycle-accurate models for performance reasons. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[3] The ITL ISA description uses decode and next_state macros, with next_state forming the core of the ISA and decode producing reusable instruction fields. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[4] The generated simulator core is a C++ class Sim, and the ITL-to-C++ translation includes generated public/private functions, architectural-state storage, type/operator replacement, and direct update overwrites. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[5] The ISS can be generated before a full RTL/ISA equivalence proof; if the ISA is updated, the ISS is regenerated, and full confidence is achieved after verification. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[6] A user-provided wrapper calls generated public functions and connects the C++ simulation core to external memories, buses, or commercial simulation/debugging tools. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[7] The C++ generation applies native type/operator mapping, optimized library functions for complex or large-bit-vector operations, shared-expression caching, intermediate-result caching, and decode-result caching. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[8] For the small pipelined processor experiment, the generated ISS achieved 7 MIPS, compared with 0.22 MIPS for an interpretive simulator and 14 MIPS for a just-in-time compiled simulator. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[9] For the industrial processor experiment, the generated ISS achieved 1.2 MIPS versus 2.5 MIPS for a commercial just-in-time compiled simulator; the design had 64 32-bit registers, a seven-stage pipeline, 88 DLX-based instructions, about 10,000 lines of VHDL, and a 2,000-line ITL property suite. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[10] The generated simulator performance is described as comparable to state-of-the-art commercial tools, while commercial JIT-CS simulators remained faster due to tool optimizations and omitted high-level hardware/pipeline effects. Generating an Efficient Instruction Set Simulator from a Complete Property Suite

[11] Using the formal property suite as the single specification source enables automatic simulator adaptation after design/specification changes and supports correct early software-development results based on instruction-set simulation. Generating an Efficient Instruction Set Simulator from a Complete Property Suite