2026-08-11
4 items 114 entities 124 connections
Processed 7 entities and 4 relations.
Processed 17 entities and 22 relations.
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
source →Processed 70 entities and 97 relations.
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors Kathryn E. Gray Gabriel Kerneis Dominic Mulligan Christopher Pulte Susmit Sarkar Peter Sewell University of Cambridge University of St Andrews IBM POWER architecture ARM architecture weakly consistent multiprocessor architectural envelope model test oracle concurrency model ISA model gem5 QEMU Sail Lem ppcmem litmus test instruction description language (IDL) out-of-order execution speculative execution MP+sync+ctrl litmus test MP+sync+rs litmus test PPOCA litmus test LB+datas+WW litmus test MP+sync+addr-cr litmus test storage subsystem model register dependency mixed-size memory access non-multicopy-atomic architecture in-flight instruction tree pre-silicon testing post-silicon testing C/C++11 concurrency TSO memory model sequentially consistent multiprocessor x86 architecture POWER ISA fixed-point non-vector user-mode instruction set Sail type system vendor pseudocode XML extraction tool Framemaker document ELF executable format OCaml executable code Coq proof assistant HOL4 Isabelle/HOL Sail interpreter instruction decode function memory barrier instruction stdu instruction stw instruction lwz instruction coherence relation register footprint analysis condition register (CR) general-purpose registers (GPR) program order undefined value semantics dynamic taint tracking exhaustive behaviour exploration Anthony Fox system_state type micro_op_state type enumerate_transitions_of_system function web interface for model exploration