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2026-08-10

4 items 78 entities 101 connections

Functional Faithfulness Verification

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Processed 14 entities and 18 relations.

Lockstep Simulation Formal Verification SupeRFIVe UVM-TLM RISC-V DPI-C Instruction Set Simulator Design Under Test Architectural State Instruction Coverage Functional Coverage Assertion-based Monitoring Pipeline Hazard Conditions RTL

Generating Distinguishing Tests using the MINION

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Processed 20 entities and 21 relations.

MINION Distinguishing Test Case Constraint Satisfaction Problem Static Single Assignment Form Loop Unrolling Mutation Testing Program Mutation Fault Localization Constraint-Based Test Data Generation Program-to-Constraint Compilation computeDistinguishingTest Algorithm Franz Wotawa Mihai Nica Bernhard K. Aichernig Technische Universität Graz CBMC Z3 SMT-solver Phi Function Variable Ordering Finite Domain

Open source and CI-driven RTL testing and verification for ...

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Processed 28 entities and 41 relations.

riscv-dv Random Instruction Generation RTL Simulation Spike Instruction Set Simulator UVM Verilator cocotb pyuvm OpenOCD GDB JTAG Functional Coverage Continuous Integration Verible RISC-V RTL VeeR Execution Trace Log Parser NOP Injection Post-Processing Script cocotb Testbench for VeeR pyuvm UVM Agent for VeeR-EL2 Programmable Interrupt Controller Lazy Parsing Stimulus Generation CHIPS Alliance Antmicro Google VeeR EL2 Custom GitHub Actions Runners

9.3 Golden Reference Models

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Processed 16 entities and 21 relations.

TestBencher Golden Reference Model Transaction-Level Model Model Under Test RTL Model Simulation Log File Stub Functions projectName_skeleton projectName_emulator projectName_emulator.h TestBuilder Library C++ Reference Model Generation VHDL Reference Model Generation Verilog Reference Model Generation Read/Write Transaction Project Generation Properties