JTAG

Concept

JTAG (Joint Test Action Group) is a hardware interface standard originally designed for system testing and boundary-scan testing of integrated circuits. Beyond its testing origins, JTAG is widely used for low-level debugging, firmware acquisition, on-chip instrumentation, and trusted forensic access to running systems. It exposes a standardized port through which tools such as OpenOCD and GDB can connect to a target for register/memory inspection, and through which on-chip data-capture logic can stream transactions off-chip for post-silicon validation and coverage analysis.

First seen 6/16/2026

Last seen 8/10/2026

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JTAG

Overview

JTAG (Joint Test Action Group) is a hardware debug and test interface standard used in microprocessors, SoCs, FPGAs, and other embedded devices. Although JTAG's main purpose is system testing (notably boundary-scan testing), it is also widely used for debugging, firmware extraction, on-chip instrumentation, and security forensics [arxiv:1512.04116v1] [opensource.googleblog.com 2023-11] [scirp 71278].

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RELATIONSHIPS

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OpenOCD ← uses 97% 1e

OpenOCD is used to connect to the VeeR design via a virtual JTAG port.

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CITATIONS

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[1] JTAG stands for Joint Test Action Group and is a hardware interface used for system testing. JoKER: Trusted Detection of Kernel Rootkits in Android Devices via JTAG Interface

[2] JTAG's main purpose is system testing, but it can also be used for malware detection where traditional methods fail. JoKER: Trusted Detection of Kernel Rootkits in Android Devices via JTAG Interface

[3] JoKER uses a device's JTAG interface to extract areas of an Android kernel's memory and reconstruct them for rootkit detection. JoKER: Trusted Detection of Kernel Rootkits in Android Devices via JTAG Interface

[4] SWD/JTAG debug-port access is one of the firmware acquisition methods evaluated on consumer drones, alongside SPI flash reading, UART capture, and clip-based contact approaches. A Multi-Interface Firmware Acquisition and Validation Methodology for Low-Cost Consumer Drones

[5] System-level tests can connect an interactive simulation via JTAG to OpenOCD and then to GDB to verify core registers, memory access, and peripheral accesses. Open source and CI-driven RTL testing and verification for Caliptra and VeeR-EL2

[6] A JTAG-based testing methodology exposed a real design bug in which the side AHB bus of the debug core was disconnected, preventing peripheral access via JTAG; joining the system and side AHB master ports with a 2-to-1 multiplexer fixed the issue. Open source and CI-driven RTL testing and verification for Caliptra and VeeR-EL2

[7] In the unified coverage methodology for SoC post-silicon validation, an On-chip Data Capturing unit communicates captured bus transactions to off-chip Coverage Analyzer software through a JTAG port. Unified Coverage Methodology for SoC Post-Silicon Validation

[8] The unified coverage methodology has been prototyped on FPGAs using Xilinx ChipScopePro ILA cores acting as the ODC, with OCA software communicating to the ODC through JTAG. Unified Coverage Methodology for SoC Post-Silicon Validation