Technique
Technique
1259 entities#
1 Lazy Page Mapping
1 2 debug mode support
1 3 formal methods for processor verification
1 4 assembly generation from JSON
1 5 random test program generation using CSP
1 6 model checking for processor test generation
1 7 random program generation
1 8 linear programming for test generation
1 9 finite state machine based test generation
1 10 graph-based test generation
1 11 genetic programming for test generation
1 12 Random Instruction Generator
1 13 Crash Trace Replay
1 14 Program generation
1 15 Specification-based test program generation
1 16 Data constraint generation
1 17 test case mutation
1 18 Reinforcement learning-based directed test generation
1 19 Coverage-Guided Graybox Fuzzing (CGF)
1 20 Directed Graybox Fuzzing (DGF)
1 21 Novelty-Driven Verification
1 22 Transition leakage
1 23 Glitch leakage
1 24 Value leakage
1 25 Evolutionary Algorithms
1 26 Genetic Algorithms
1 27 Assembly-level test program generation
1 28 Formal specification-driven test generation
1 29 CSR-guided processor fuzzing
1 30 Finite state machine state transition identification
1 31 Cycle-sensitive register coverage guiding
1 32 Asynchronous interrupt events handling
1 33 Unified CPU input format with TileLink protocols
1 34 Drop-in-replacement designs
1 35 PowerPC verification methodology
1 36 Stuck-At Fault Coverage
1 37 Hybrid Intelligent Testing
1 38 wrapper-class randomization
1 39 Test-Driven Development
1 40 Direct Test Verification
1 41 Bayesian Network Test Generation
1 42 N-Version Disassembly
1 43 Dynamic Instruction Generation
1 44 Weight-Based Transaction Control
1 45 Data Comparison via Backdoor Read
1 46 Unaligned Address Testing
1 47 AXI Transaction ID Randomization
1 48 Seed-Based Regression Grading
1 49 Bayesian Networks for Test Generation
1 50 Evolutionary Assembly Program Generation
1 51 Ordered Binary Decision Diagrams (BDDs)
1 52 Grammatical Evolution
1 53 arc consistency
1 54 Checkpoint and Seed Logging
1 55 UVM-based Random Instruction Generation
1 56 logic gate shadow logic instrumentation (GLIFT)
1 57 Deduction-Guided Reinforcement Learning
1 58 Conflict-Driven Learning
1 59 RTLIFT
1 60 Functional Built-In Self Test
1 61 Memory Concurrency Testing
1 62 LLM-aided FPGA Parallelism
1 63 Lowered VIAM
1 64 C-Code Generation
1 65 BDD solving for constraint randomization
1 66 differential symbolic execution
1 67 SMT Solver-Based Test Generation
1 68 sequential randomization of instruction fields
1 69 Array Constraints with foreach Construct
1 70 Dynamic Test Compaction
1 71 Static Test Compaction
1 72 hazard handling
1 73 Random Instruction Stream
1 74 random branch instruction generation
1 75 Burch-Dill Verification Method
1 76 Boolean Satisfiability Checking
1 77 Symbolic QED
1 78 SystemVerilog foreach Array Constraints
1 79 illegal instruction generation
1 80 Feedback-Driven Generation
1 81 Scoreboard-based Verification
1 82 Reference Prediction Model
1 83 Constraint Satisfaction
1 84 MMU stress testing
1 85 Memory Access Generation
1 86 Address Constraint Satisfaction
1 87 Constraint-Based Automatic Test Data Generation
1 88 user-defined coverage
1 89 Belief Network Constraint Conversion
1 90 Coverage Testing
1 91 Randomized Stimulus Generation
1 92 Functional Testing
1 93 Symbolic Model Checking
1 94 Joint Random Collision Generation
1 95 HCL Control Logic Description
1 96 Pipeline Flushing
1 97 Hybrid Fuzzer Integration
1 98 Integer Programming
1 99 genetic approach to automatic bias generation
1 100 silicon testing
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