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STIMSMITH
Technique

Technique

1157 entities
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1
sliding mutation engine
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Stimulus Serialization
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Uninterpreted Functions with Equality
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Abstract Transfer Function Derivation
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Axiomatic Hardware-Software Contracts
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Power Scheduling
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Binary Search for Address Filtering
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Meta-Tracing JIT Compilation for ISS
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multi-pass comparison checking
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Instruction Set Simulator Generation
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Single Static Assignment (SSA)
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Dynamic Binary Translation
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Static Binary Compilation for Noise Removal
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feature randomization
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Pseudocode-to-Formal-Semantics Translation
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mark_vs_dirty
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ldst_us_trans
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ldst_stride_trans
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ldst_index_trans
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ldst_whole_trans
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LLM Fine-tuning for RTL
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custom tracer for execution log capture
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DPI-based Synchronization
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Random Pattern Simulation
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Sequential Instruction Field Randomization
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Difference-based Testing
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Trace-Based Verification
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Counterexample Reduction
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FSM traversal based test generation
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Unsat Core Computation
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counter-example guided synthesis
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Ackermannization
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Partition Testing
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Shrinking
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intricate program generation for CPU fuzzing
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diverse instruction construction
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Property Based Testing
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Cell-Based Genetic Algorithm (CGA)
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co-simulation for processor fuzzing
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Retargetable Code Generation
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Constraint Logic Programming (CLP)
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Biased-Random Simulation
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unordered floating-point reduction reference model
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Hierarchical Learning
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Explainable AI (XAI)
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Transfer Learning
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Magic Instruction Generation
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Instruction Shuffle
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machine learning-based test generation
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Formal Property Checking via RVFI
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instruction-set simulation
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syntax-aware test case generation
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Zeng, Z.
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Sliding Window Fuzzing Strategy
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Real-world benchmarks
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OVM (Open Verification Methodology)
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dynamic instrumentation
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Stimulus Graphs
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instruction generation coverage model
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Reinforcement Learning for Proof Generation
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Formal Methods
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Property-Based Verification
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interpretation
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stimulus-driven hardware fuzzing
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model-based input generation
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grammar-based input generation
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Assertions
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Transaction-Based Verification
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Dynamic Interpolation Framework
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Verification Planning
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Abstract Interpretation
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Direct Preference Optimization
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template placement algorithm
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just-in-time translation
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constraint backtracking search
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CSV-based log comparison scripts
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Andersen's Algorithm
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Directed Random Verification
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Mutation Adequacy
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debug mode support
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Dynamic Biased Pseudo-Random Test Program Generation
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Test Program Generation for Functional Verification
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BDD-Based Sampling
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Tseitin Encoding
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Virtual Prototype Verification
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random branch instruction generation
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SystemVerilog Interface
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Modport
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Clocking Block
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Maximally Diverse Interpretations
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Signal Direction Control
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Timing Abstraction
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Reduction to Propositional Logic
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Constrained Random Stimulus
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Instruction Trace Comparison
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illegal instruction generation
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random instruction sequence generation
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Lazy Page Mapping
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hardware fuzz testing
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language model-based fuzzer
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