Technique
Technique
1157 entities#
1 runtime detection
1 2 microcode-level instrumentation
1 3 microarchitectural introspection
1 4 microcode patching
1 5 Branch Coverage
1 6 information flow tracking
1 7 Scoreboard-based Verification
1 8 Reference Prediction Model
1 9 Constraint Satisfaction
1 10 retrieval-augmented generation
1 11 Memory Access Generation
1 12 Address Constraint Satisfaction
1 13 Constraint-Based Automatic Test Data Generation
1 14 Custom UVM Factory
1 15 SMT Solver-Based Test Generation
1 16 coverage driven simulation
1 17 Semi-Formal Verification
1 18 Particle Swarm Optimization (PSO)
1 19 Constraint-Based Initial Value Generation
1 20 Dynamic Test Compaction
1 21 Static Test Compaction
1 22 Window Training Packet
1 23 Linear-Feedback Shift Register (LFSR)
1 24 virtual prototyping
1 25 Dictionary-Based Mutation
1 26 Static Verification
1 27 user-defined coverage
1 28 Auto-Regression
1 29 Belief Network Constraint Conversion
1 30 Coverage Testing
1 31 Randomized Stimulus Generation
1 32 Functional Testing
1 33 Symbolic Model Checking
1 34 functional equivalence checking
1 35 Ant Colony Optimization (ACO)
1 36 Hybrid hardware fuzzing
1 37 Seed generation
1 38 Stochastic Search
1 39 Directed graybox fuzzing
1 40 Joint Random Collision Generation
1 41 Register Scrambling
1 42 Constrained Random Instruction Stream Generation
1 43 genetic approach to automatic bias generation
1 44 silicon testing
1 45 random test input generation
1 46 Nondeterminism Elimination
1 47 Bayesian Network Test Generation
1 48 regular expression filtering
1 49 power level transition testing
1 50 two-phase evolution of variable length tests
1 51 artificial neural network for test acceleration
1 52 ID3 Algorithm
1 53 C4.5 Algorithm
1 54 Bayesian network for coverage modeling
1 55 Checkpoint-Based Regression
1 56 Non-Deterministic Source Masking
1 57 Seed-Based Deterministic Replay
1 58 Fuzzing for Test Generation
1 59 Static Backward Slicing
1 60 mean square error loss for coverage prediction
1 61 Structured RISC-V Tokenizer
1 62 Random Network Distillation
1 63 hardware-assisted validation
1 64 DPI-C
1 65 positional encoding
1 66 LSTM for instruction sequence modeling
1 67 bus cycle delay randomization
1 68 Recurrent Neural Network-Based Constraint Alteration for PRG
1 69 Dynamic Simulation
1 70 Symbolic Instruction Graphs
1 71 Formal Property Verification (FPV)
1 72 Automatic Test Program Generation for Pipelined Processors
1 73 SystemVerilog-based Verification
1 74 Sampling&Filtering Mechanism
1 75 SAT-solver-based test generation
1 76 CorrectVal Generation
1 77 Signature Register Allocation
1 78 Parallel Test Generation
1 79 Variant Ant Colony Optimization
1 80 Source-Based Code Coverage
1 81 Multi-Core Validation
1 82 Random Solver
1 83 C++ Reference Model Generation
1 84 VHDL Reference Model Generation
1 85 Verilog Reference Model Generation
1 86 Unit Testing
1 87 MC/DC coverage
1 88 random test
1 89 boundary condition test
1 90 random constrained test
1 91 Bayesian network stimulus generation
1 92 BNF-based Test Program Generation
1 93 Constraint Satisfaction-based Test Generation
1 94 Graph Representation
1 95 Application Compilation
1 96 branch-and-bound optimization
1 97 Asynchronous Programming
1 98 RACE Solver
1 99 Subgraph Isomorphism
1 100 constraint-based generator
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