Automatic Test Program Generation for Pipelined Processors

Technique

A processor verification technique introduced by Iwashita, Kowatari, Nakata, and Hirose at ICCAD 1994, in which test programs are generated automatically to validate pipelined processor implementations, cited alongside simulation-based and formal methods for architecture and pipeline-interlock validation.

First seen 8/1/2026

Last seen 8/1/2026

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Overview

Automatic Test Program Generation for Pipelined Processors is a design-verification technique for processor implementations. It was introduced in:

H. Iwashita, S. Kowatari, T. Nakata, F. Hirose, "Automatic Test Program Generation for Pipelined Processors," Proceedings of the International Conference on Computer Aided Design, November 1994. (Google Scholar)

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Automatic Test Program Generation for Pipelined Processors ← introduces 100% 1e

The paper introduces automatic test program generation for pipelined processors.

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CITATIONS

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[1] The technique was introduced by H. Iwashita, S. Kowatari, T. Nakata, and F. Hirose at the International Conference on Computer Aided Design in November 1994. A methodology for processor implementation verification | Springer Nature Link

[2] The technique is grouped in the processor-verification literature with formal/simulation-based verification of microprocessors (Beatty & Bryant, 1994), architecture validation (Ho et al., 1995), systematic pipeline-interlock validation (Diep & Shen, 1995), and prior integrated design-and-test work for pipeline controllers by Iwashita, Nakata, and Hirose (IEICE 1993). A methodology for processor implementation verification | Springer Nature Link