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Automatic Test Program Generation for Pipelined Processors

Technique WIKI v1 · 8/1/2026

A processor verification technique introduced by Iwashita, Kowatari, Nakata, and Hirose at ICCAD 1994, in which test programs are generated automatically to validate pipelined processor implementations, cited alongside simulation-based and formal methods for architecture and pipeline-interlock validation.

Overview

Automatic Test Program Generation for Pipelined Processors is a design-verification technique for processor implementations. It was introduced in:

H. Iwashita, S. Kowatari, T. Nakata, F. Hirose, "Automatic Test Program Generation for Pipelined Processors," Proceedings of the International Conference on Computer Aided Design, November 1994. (Google Scholar)

The technique targets the validation of pipelined processor designs by programmatically producing test programs, rather than relying solely on hand-written tests, simulation, or formal proofs.

Provenance and Related Work

Within the citation graph of processor-implementation verification, the Iwashita et al. ICCAD 1994 paper is grouped with related approaches that address different facets of the same problem:

  • Architecture validation — Ho, Yang, Horowitz, and Dill, "Architecture Validation for Processors," ACM ISCA, 1995.
  • Formal simulation-based verification of a microprocessor — D. L. Beatty and R. E. Bryant, "Formally Verifying a Microprocessor Using a Simulation Methodology," ACM/IEEE DAC, 1994.
  • Systematic pipeline-interlock validation for superscalar microarchitectures — T. A. Diep and J. P. Shen, "Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures," 25th Annual International Symposium on Fault Tolerance, June 1995.
  • Integrated design and test for pipeline controllers (predecessor work by the same authors) — H. Iwashita, T. Nakata, F. Hirose, "Integrated Design and Test Assistance for Pipeline Controllers," IEICE Transactions on Information Systems (Japan), Vol. E76-D, No. 7, July 1993.
  • Reference architectures used as verification targets — C. May, E. Silha, R. Simpson, H. Warren (eds.), The PowerPC Architecture, Morgan Kaufmann, 1994; S. Weiss and J. E. Smith, POWER and PowerPC, Morgan Kaufmann, 1994.
  • Industrial processor-implementation verification methodology — D. Lewin, D. Lorenz, S. Ur, "A Processor Implementation Verification Methodology," IBM Unpublished Document.

The Springer chapter "A methodology for processor implementation verification" (link.springer.com/chapter/10.1007/bfb0031804) cites the Iwashita et al. ICCAD 1994 paper as one of the test-program-generation approaches used to validate pipelined processors, placing it within a broader taxonomy of processor-verification techniques that includes formal verification (Ho et al., Beatty & Bryant), interlock-specific validation (Diep & Shen), and prior integrated design/test work by Iwashita, Nakata, and Hirose (1993).

References

  1. H. Iwashita, S. Kowatari, T. Nakata, F. Hirose, "Automatic Test Program Generation for Pipelined Processors," ICCAD, November 1994.
  2. H. Iwashita, T. Nakata, F. Hirose, "Integrated Design and Test Assistance for Pipeline Controllers," IEICE Trans. Information Systems (Japan), Vol. E76-D, No. 7, July 1993.
  3. D. L. Beatty, R. E. Bryant, "Formally Verifying a Microprocessor Using a Simulation Methodology," ACM/IEEE DAC, 1994.
  4. T. A. Diep, J. P. Shen, "Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures," 25th Int'l Symp. on Fault Tolerance, June 1995.
  5. Ho, C. Han Yang, M. A. Horowitz, D. L. Dill, "Architecture Validation for Processors," ACM ISCA, 1995.
  6. D. Lewin, D. Lorenz, S. Ur, "A Processor Implementation Verification Methodology," IBM Unpublished Document.
  7. C. May et al. (eds.), The PowerPC Architecture, Morgan Kaufmann, 1994.
  8. S. Weiss, J. E. Smith, POWER and PowerPC, Morgan Kaufmann, 1994.
  9. "A methodology for processor implementation verification," Springer Nature Link.

LINKED ENTITIES

1 links
Automatic Test Program Generation for Pipelined Processors INTRODUCES

CITATIONS

2 sources
2 citations
[1] The technique was introduced by H. Iwashita, S. Kowatari, T. Nakata, and F. Hirose at the International Conference on Computer Aided Design in November 1994. A methodology for processor implementation verification | Springer Nature Link
[2] The technique is grouped in the processor-verification literature with formal/simulation-based verification of microprocessors (Beatty & Bryant, 1994), architecture validation (Ho et al., 1995), systematic pipeline-interlock validation (Diep & Shen, 1995), and prior integrated design-and-test work for pipeline controllers by Iwashita, Nakata, and Hirose (IEICE 1993). A methodology for processor implementation verification | Springer Nature Link