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CSR-guided processor fuzzing

Technique

CSR-guided processor fuzzing is a processor fuzzing technique identified in the paper "ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance." The available evidence supports that it uses control and status registers (CSRs) as guidance and that the work was published at IEEE HOST 2023.

First seen 6/28/2026
Last seen 6/28/2026
Evidence 1 chunks
Wiki v1

WIKI

CSR-guided processor fuzzing is a processor fuzzing technique whose distinguishing characteristic, based on the available evidence, is guidance from control and status registers (CSRs).[1]

Overview

The technique is directly associated with the paper ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance.[1] From the title alone, the evidence supports describing this technique as processor fuzzing guided by control and status registers.[1]

Publication

The cited work is:

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections
The work proposes a processor fuzzing approach guided by Control and Status Registers (CSR).
ProcessorFuzz ← implements 68% 1e
ProcessorFuzz embodies a CSR-guided variant of processor fuzzing.
Control and Status Registers (CSR) uses → 74% 1e
The CSR-guided processor fuzzing technique relies on CSRs to guide fuzzing.
Processor Fuzzing extends → 65% 1e
CSR-guided processor fuzzing is a specialized form of general processor fuzzing.

CITATIONS

3 sources
3 citations — click to collapse
[1] CSR-guided processor fuzzing is a processor fuzzing technique guided by control and status registers (CSRs). ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance - researchr publication
[2] The technique is associated with the paper "ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance." ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance - researchr publication
[3] The paper was published in IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2023), pages 1-12, in 2023. ProcessorFuzz: Processor Fuzzing with Control and Status Registers Guidance - researchr publication