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Cycle-sensitive register coverage guiding

Technique

Cycle-sensitive register coverage guiding is a technique developed in DIFUZZRTL for RTL fuzzing of CPU designs. In the DifuzzRTL paper, it is presented as one of several techniques added to address RTL-specific characteristics, alongside register-coverage guided fuzzing, asynchronous interrupt event handling, a unified CPU input format with Tilelink protocols, and drop-in-replacement designs for multiple CPU RTLs.

First seen 6/28/2026
Last seen 6/28/2026
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Cycle-sensitive register coverage guiding

Cycle-sensitive register coverage guiding is an RTL fuzzing technique described in the paper DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs and used in DIFUZZRTL. The paper presents it as one of several methods introduced to account for the distinctive characteristics of RTL CPU designs.[1][2]

Context in DIFUZZRTL

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RELATIONSHIPS

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Cycle-sensitive register coverage guiding is introduced as part of the new techniques.
DiFuzzRTL ← implements 96% 1e
DIFUZZRTL includes cycle-sensitive register coverage guiding to handle RTL timing aspects.

CITATIONS

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4 citations — click to collapse
[1] DIFUZZRTL is an RTL fuzzer for automatically discovering unknown CPU RTL bugs. DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
[2] DifuzzRTL includes cycle-sensitive register coverage guiding as an RTL-specific technique. DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
[3] DIFUZZRTL develops register-coverage guided fuzzing to identify RTL state transitions. DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs
[4] Cycle-sensitive register coverage guiding is presented alongside asynchronous interrupt event handling, a unified CPU input format with Tilelink protocols, and drop-in-replacement designs for supporting various CPU RTLs. DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs