Concept
Concept
4823 entities#
1 Lock-Step Compare
2 2 Prefetch Buffer
2 3 Instruction Decode (ID) stage
2 4 x86_64 instruction format
2 5 SPLASH-2 benchmarks
2 6 Coverage-guided Aging Counter
2 7 generate_directed_instr_stream function
2 8 Instruction Memory (IMem)
2 9 data-flow coverage
2 10 Conservative Approximation
2 11 Dynamic Array
2 12 Load-Reserved/Store-Conditional instructions
2 13 CANbus Protocol
2 14 Single Group Mapping
2 15 Genetic Programming
2 16 WARL (Write Any Read Legal)
2 17 Dynamic Bin Mapping
2 18 RISC-V instruction sequence generation
2 19 Instruction Opcode Class Hierarchy
2 20 Structural Coverage-Based Fuzzing
2 21 Floating-Point Control and Status Register
2 22 vDSO
2 23 Instruction Issue (IS) stage
2 24 Jupyter notebooks
2 25 interrupt stimulus
2 26 vmm_data
2 27 bounded load/store operations
2 28 Coverage Bins
2 29 Privilege Levels in RISC-V
2 30 Fault Reporting Issue
2 31 Seed Selection
2 32 vstart value
2 33 illegal instruction trap
2 34 instruction blacklisting
2 35 Transistor-Level Verification
2 36 Assumption-based Pruning
2 37 CompareForContainment Function
2 38 regression suite
2 39 ALU Constraint Verification
2 40 Simulation-based Equivalence Checking
2 41 Execution Runner
2 42 executable semantics
2 43 Machine Learning for Fuzzing
2 44 Library Protection
2 45 Microarchitectural state divergence
2 46 glitchy_decode
2 47 Five-Stage Pipeline CPU
2 48 Abstract Graph Description
2 49 Symbolic Binary Simulation
2 50 input instruction sequence
2 51 processor control path verification
2 52 interrupt and exception handling
2 53 processor data path verification
2 54 CISC CPU
2 55 Machine Learning for Test Generation
2 56 Ontology
2 57 epex-formal-rv32-model
2 58 Branch Scenario Generation
2 59 Exceptions and Interrupts
2 60 Instruction Statement
2 61 Program Input Generation
2 62 Scenario Generator
2 63 eBPF Bytecode Test
2 64 special purpose registers
2 65 Unreachable State Identification
2 66 CSP/SMT Solver
2 67 Wasm Validator
2 68 Data Dependency Analysis
2 69 Randomized Test Strategy
2 70 Instruction Group Coverage Points
2 71 Opcode Generator
2 72 Kernel Memory Leak
2 73 higher-order logic
2 74 Formal Verification Methods
2 75 host-FPGA communication overhead
2 76 Control Expression (CExpr)
2 77 ebpf-for-windows
2 78 Clock Glitch
2 79 Memory Protection Unit
2 80 Register Type Pool
2 81 Morphing Map
2 82 Linux ARM32 eBPF Implementation
2 83 Morello
2 84 RSH Instruction
2 85 Electromagnetic Pulse
2 86 Inevitable State
2 87 Multicore Parallelism
2 88 safe speculation
2 89 capability mode bit
2 90 Intermediate Code Representation (ICR)
2 91 Test Manager
2 92 instruction pipeline
2 93 bounds checking
2 94 CHERIvoke
2 95 Integrated Circuit (ASIC) Design
2 96 tag controller
2 97 ISA-Level Instruction Generation
2 98 merged register file
2 99 assembly program test input
2 100 Register
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