Concept
Concept
2130 entities#
1 load instruction generation
1 2 add_directed_instr_stream
1 3 Soft-CSP
1 4 Portable Stimulus Standard
1 5 coverpoints
1 6 covergroups
1 7 program level randomization
1 8 sequence level randomization
1 9 instruction level randomization
1 10 hardware-software co-debug
1 11 get_directed_instr_stream
1 12 Pipeline Consistency Predicate
1 13 RTL-based Sampling
1 14 Program Emulator
1 15 Hardware Simulation Binary
1 16 Model Driven Architecture
1 17 Signal Reference Result
1 18 Template of Testbench
1 19 Consistent Outputs
1 20 Template of MetaFuzz
1 21 UCLID5 Verification Condition (correspondence invariant)
1 22 Outlier Detection
1 23 multithreaded scenario generation
1 24 maintaining arc consistency
1 25 Partial Consistent
1 26 LLM-as-a-Judge
1 27 Self-Improvement Sampling
1 28 natural language processing
1 29 RTL Input Instructions
1 30 Random Stimuli Generation
1 31 GELU activation function
1 32 Solution Space Elaboration
1 33 Directed Random Stimulus
1 34 Red-Unlock mode
1 35 bare-metal hypervisor-based fuzzing framework
1 36 serialization oracle
1 37 performance counters
1 38 randomly initialised data in dmem
1 39 Direct Programming Interface (DPI)
1 40 Makefile
1 41 Actor-Critic
1 42 Spectre-V1
1 43 Regression Test Stimulus Isolation
1 44 Information leakage
1 45 Foreshadow
1 46 riscv_instr_base_test
1 47 Exploration-Exploitation Tradeoff
1 48 Conditional CSP
1 49 IBM Power processor
1 50 Property Formulation
1 51 Program-Based Stimuli
1 52 Production Rules (Events)
1 53 Closed-Loop Instruction Generation
1 54 Multi-Input Policy
1 55 Processor Data Path
1 56 Processor Control Path
1 57 Window Training Packet
1 58 feedback-based coverage directed test generation
1 59 Large Domain Variables
1 60 Bit Vector Stimuli
1 61 UCLID5 Pipeline Register Definition
1 62 Transient Execution Vulnerability Detection
1 63 Deeptrans Address Translation Verification
1 64 Architectural Validity Rules
1 65 Implementation Verification Program
1 66 Huge Domains in CSP
1 67 Huge Domain Constraint Propagation
1 68 Hardware Design Cycle
1 69 assembly listing
1 70 program size parameter
1 71 Cooperative Threading
1 72 Behavioral Simulator
1 73 Hardware Simulator
1 74 Resource Manager
1 75 Context Switching
1 76 Expert Systems
1 77 Directed Random Stimuli Generation
1 78 core_ibex_test_lib.sv
1 79 calculus of inductive constructions
1 80 FIRRTL
1 81 binary decoder
1 82 opcode distribution and biasing
1 83 NaN-boxing
1 84 Random Test Program Generation
1 85 TheHuzz
1 86 Register Reloading Technique
1 87 Coremark benchmark
1 88 Processor Testbench
1 89 Illegal Opcode Exception
1 90 Hardware-accelerated Verification
1 91 Test Case Quality
1 92 Backward Data-flow Analysis
1 93 Functional Safety Verification
1 94 Randomised Tandem Verification
1 95 Control Logic Abstraction
1 96 ISO-C 99 standard
1 97 ARM reference manual pseudo-code extraction
1 98 blackbox
1 99 Register Allocation Policy
1 100 faults check
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