Binary Decoder

Concept

A binary decoder, in the context of instruction set simulation (ISS), is a component that translates binary machine-code instructions into structured intermediate representations (such as C structures) so that a simulator or dynamic translator can execute them. In systems such as SimSoC, the binary decoder is an integral part of dynamic binary translation pipelines for embedded processors like the ARMv6 architecture.

First seen 6/7/2026

Last seen 6/7/2026

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Binary Decoder

Overview

In instruction set simulation (ISS) and dynamic binary translation, a binary decoder is the component responsible for converting a stream of raw binary machine instructions fetched from memory into an internal, structured representation that the rest of the simulator can interpret and execute. The decoder is the "decoded" step of the classical fetch–decode–execute cycle used in interpretive simulation [1].

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RELATIONSHIPS

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Towards Verified Faithful Simulation ← uses 85% 1e

The paper assumes existence of a correct decoder

LINKED ENTITIES

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Towards Verified Faithful Simulation USES Extracted graph relationship

instruction-set simulation PART_OF The evidence describes the binary decoder as performing the 'decoded' step of the fetch–decode–execute cycle used in interpretive ISS implementations.

CompCert SUPPORTED_BY The evidence explains that the formal verification surrounding the binary decoder relies on the CompCert Coq library for words, bytes, and bitwise operations, and on CompCert's C operational semantics.

CITATIONS

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7 citations — click to expand

[1] In interpretive simulation, each instruction of the target program is fetched from memory, decoded, and executed; the binary decoder performs the decoding step. Towards Verified Faithful Simulation

[2] Most ISS implementations use some kind of dynamic binary translation, initiated with systems such as Embra. Towards Verified Faithful Simulation

[3] SimSoC is a full system simulator of System-on-Chips that takes real binary code as input and simulates the processor, memory units, interconnect, peripherals, and a network controller. Towards Verified Faithful Simulation

[4] In the first dynamic-translation mode of SimSoC, the binary decoder translates each instruction into a C structure that has a semantics function. Towards Verified Faithful Simulation

[5] The proof assumes the existence of a correct decoder to dynamically generate the translation of the input binary into C structures, translating the binary input sequence into a sequence of qualified instructions, and this decoding step is out of scope of the proof. Towards Verified Faithful Simulation

[6] SimSoC's ARMv6 ISS uses the SystemC kernel to simulate hardware parallelism and Transaction Level Modeling (TLM) to model inter-module communications. Towards Verified Faithful Simulation

[7] The verification uses the CompCert Coq library for words, half-words, bytes, and bitwise operations, whose properties have already been proven in CompCert and can be re-used. Towards Verified Faithful Simulation