Concept
Concept
4932 entities#
1 formal semantics
3 2 Instruction Map
3 3 Trigger Training Packet
3 4 program non-termination as bug detection
3 5 LSTM
3 6 Multi-Group Mapping
3 7 Covariance Matrix
3 8 constraint-based random stimulus generation
3 9 Input Grammar
3 10 Fuzzing Coverage
3 11 ISA compliance
3 12 Secret Encoding
3 13 Multivariate Normal Distribution
3 14 Machine Programming
3 15 ePMP
3 16 opcode::byte_pack()
3 17 latency-aligned group-coverage
3 18 opcode::psdisplay()
3 19 RISC-V Sail specification model
3 20 RISC-V FP extensions (F, D, Zfh)
3 21 Load Fill Buffer
3 22 test case completion
3 23 RISC-V compliance test suite
3 24 Foreshadow
3 25 Bubble Sort Input Generation
3 26 Spectre-V2
3 27 PCI Bus
3 28 Over-constraint Analysis
3 29 Safety Property
3 30 constrained random test bench for ARM AMBA
3 31 Operand
3 32 State Machine Model
3 33 Privileged ISA
3 34 Assembly Program Generation
3 35 constrained random test bench for IBM CoreConnect
3 36 rand_vec<T>
3 37 ALU Abstraction Modeling
3 38 Control Flow Over-Tainting
3 39 self-checking code
3 40 System-Level Testing
3 41 pseudorandom code generation
3 42 Global Constraints
3 43 Dynamic Constraint Management
3 44 x language
3 45 Random Number Generator
3 46 Digital Signal Processing
3 47 Spectre-RSB
3 48 Inline Constraints
3 49 EIT Architecture
3 50 Instruction-Level Unit Testing
3 51 reservation station
3 52 performance counters
3 53 Mapping Function
3 54 Electronic System Level Design
3 55 x86_64 Instruction Encoding
3 56 Invalid+Valid Sequences (IVS) test set
3 57 AES Key Schedule
3 58 sub-unit RTL verification
3 59 Test Case Refinement
3 60 add.rm.ftz.sat.f32 C semantics
3 61 simple test actions
3 62 data hazards
3 63 Instruction Block Concatenation
3 64 Vulnerability Discovery
3 65 Valid Sequences (VS) test set
3 66 CodeCheckRunner
3 67 Test Template
3 68 Sandboxing
3 69 Concretization
3 70 ISA-compliant Test Generation
3 71 Faulty Transition System
3 72 Sail language
3 73 RISC-V Vectors Extension
3 74 Reachability Property
3 75 Natural Language Specification
3 76 Order Dependent Instructions
3 77 test sequence tokenization
3 78 instruction window
3 79 Code Fragment
3 80 Functional Test Program
3 81 instruction embedding
3 82 undefined behaviour
3 83 PTX instruction set
3 84 Design for Testability (DfT)
3 85 model-based test case generation
3 86 CPU processor design
3 87 path coverage criterion
3 88 array constraints
3 89 Marginal Defects
3 90 Non-functional Properties
3 91 Source Instrumentation
3 92 Per-Instruction Logging
3 93 Error Correction Code (ECC)
3 94 multiplexer select signal
3 95 Branch Target Buffer (BTB)
3 96 storage subsystem model
3 97 Functional Safety
3 98 program order
3 99 TileLink protocol
3 100 Instruction Generator (InstrGen)
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