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STIMSMITH
Concept

Concept

4932 entities
#
1
Hierarchical Code Composition
2
2
context-free grammar
2
3
Compiler Testing
2
4
Selective Testing
2
5
Python bindings
2
6
Top of Range (TOR)
2
7
end-of-simulation comparison
2
8
Stencil Computation
2
9
Implication Operator in Constraints
2
10
If-Else Constraint Construct
2
11
Constant vs Variable in Constraint
2
12
false positive detection
2
13
Randomized Tests
2
14
Load-Reserved Store-Conditional
2
15
Task Graph
2
16
Architectural Testing
2
17
ISA Coverage Specification
2
18
Assembler
2
19
Random Variable Distribution
2
20
labeling phase
2
21
transient execution vulnerabilities
2
22
Signature-Based Testing
2
23
Data Propagation Analysis
2
24
ISA scope
2
25
inside Operator
2
26
USB peripheral
2
27
INTERPRETER_exec()
2
28
ASIC Design
2
29
APU_t struct
2
30
Dynamic Voltage and Frequency Scaling
2
31
Constraint-Based Random Test Generation
2
32
direct-memory-access (DMA)
2
33
Meltdown attacks
2
34
solution space projection
2
35
SoC Generation Framework
2
36
GPU Kernel
2
37
interrupt stimulus
2
38
Fault Localization
2
39
outlier bugs
2
40
N-Queens Problem
2
41
End State Recording
2
42
POWER Architecture
2
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test controller
2
44
Assertion Coverage
2
45
CGF Format
2
46
Instruction Group Cross-product Coverage Points
2
47
op_gen.sv
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48
system element behavior
2
49
mispredicted path fuzzing
2
50
Instruction Fusion
2
51
IEEE 754 standard
2
52
Async TLM FIFO
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Dual Issue Pipeline
2
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Pipeline Follower
2
55
cache miss generation
2
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TLM Analysis Ports
2
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End-to-End Verification
2
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endianness vulnerability
2
59
ROM firmware
2
60
Exponential State Space Growth
2
61
DV document
2
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DIF
2
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IP Core
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64
Lookup Table (LUT)
2
65
ISS
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Coverage-guided Greybox Fuzzing
2
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Armv8-A ISA
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RISC-V Binary (ELF)
2
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Burch-Dill Flushing Refinement
2
70
Aurora-Fuzz Configuration Script
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instruction fetch matching algorithm
2
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RISC-V Assembly
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riscv_instr_base_test
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UVC
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Chain of Thought Prompting
2
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Program of Thoughts
2
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Activity Constraint
2
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condition code matching
2
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armshaker.py front-end
2
80
Trace Equivalence
2
81
array constraint handling
2
82
Uniform Stimulus Generation
2
83
HMAC
2
84
Microarchitectural Model
2
85
SPLASH-2 benchmarks
2
86
Interrupt and Exception Unit
2
87
GRPO-SMu training dataset
2
88
Cache Side-Channel Attack
2
89
user defined rules
2
90
event behavior rules
2
91
ADDC instruction
2
92
Ethernet Frame
2
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testbench template
2
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carry bit
2
95
ISA-level Test Program Generation
2
96
Path Selection in FSM
2
97
Model Context Protocol
2
98
Open-Source Hardware
2
99
ReAct
2
100
Header Checksum
2
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