RISC-V Assembly Program Generation

Concept

RISC-V assembly program generation in RISCV-DV produces bare-metal RISC-V assembly programs, or in some modes executable memory-loadable dumps, for RISC-V processor and model verification. The flow is configurable through randomized generator configuration and command-line parameters, constructs main and optional sub-program instruction streams, inserts directed streams for sequenced scenarios, emits program sections such as initialization, data, stack, page-table, and trap-handling code, and converts randomized instruction streams into assembly text.

First seen 5/25/2026

Last seen 5/28/2026

Evidence 3 chunks

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Overview

RISC-V assembly program generation, as described for RISCV-DV, is the process of producing a complete bare-metal RISC-V assembly language test program for processor verification. The generated program can be compiled and executed on a RISC-V processor core or model. RISCV-DV can also generate an executable dump that may be loaded directly into memory for simulation or emulation; in the SystemVerilog version, this dump is represented as ASCII text because SystemVerilog does not provide native binary-data processing support. ^[1]

In the RISCV-DV implementation, the riscv_asm_program_gen.sv class is the central SystemVerilog/UVM component responsible for generating the full assembly program. The generated ASM program includes sections such as initialization, instruction, data, stack, page table, interrupt handling, and exception handling, with those sections produced by functions in riscv_asm_program_gen. ^[2]

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RELATIONSHIPS

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riscv-dv ← implements 100% 2e

riscv-dv generates complete RISC-V assembly programs for verification.

riscv_asm_program_gen ← implements 100% 2e

riscv_asm_program_gen is the main class responsible for generating complete RISC-V assembly programs.

gen_program ← implements 100% 2e

gen_program is the main orchestration function implementing full RISC-V assembly program generation.

riscv-dv ← introduces 100% 1e

RISCV-DV outputs a bare-metal RISC-V assembly language program.

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riscv_asm_program_gen IMPLEMENTS Extracted graph relationship

CITATIONS

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9 citations — click to expand

[1] RISCV-DV outputs a bare-metal RISC-V assembly program, can also generate an executable memory-loadable dump, and the SystemVerilog version outputs ASCII instead of native binary data. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] `riscv_asm_program_gen.sv` is the RISCV-DV class responsible for generating complete RISC-V assembly programs and their major sections. RISC-V source class riscv_asm_program_gen, the brain behind ...

[3] `riscv_instr_gen_config` randomization controls extensions, privilege mode, instruction counts, and suppression controls such as `no_ebreak`, `no_dret`, `no_fence`, and `no_wfi`. RISC-V source class riscv_asm_program_gen, the brain behind ...

[4] RISCV-DV generation is customizable through command-line options including sub-program counts and instruction-stream ratios; it can emit random instructions into a main function or divide them across sub-programs with function-call control flow. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] `gen_program()` invokes helper functions to generate headers, initialize GPRs, generate directed streams, convert instruction streams to assembly, insert sub-programs, add host-interface code, and prepare trap-handling support. RISC-V source class riscv_asm_program_gen, the brain behind ...

[6] RISCV-DV uses directed streams for sequenced execution scenarios such as loop sequences, load/store hazards, and numeric computation exceptions, and avoids unsafe unconstrained jumps such as problematic `jalr` placement. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] Directed streams are generated, randomized, inserted into non-directed randomized instructions without nesting inside already-inserted directed streams, and jump targets are labeled near the end of generation. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] The generated program contains randomized instructions and GPR selections suitable for RISC-V IP verification. RISC-V source class riscv_asm_program_gen, the brain behind ...

[9] RISCV-DV runtime varies with selected parameters, and `uvm_trace` can be used to record wall-clock timing around code regions for profiling. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings