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STIMSMITH
Concept

Concept

4823 entities
#
1
Abstract Interpretation
2
2
Instruction-Level Abstraction
2
3
Hypervisor Verification
2
4
Instruction Set Processor (ISP) Description
2
5
Reorder Buffer Monitoring
2
6
Forwarding Structure Testing
2
7
Fetch and Commit Trace Merging
2
8
Speculative Fetch Detection
2
9
ELF File Execution
2
10
Qwen LLM Family
2
11
StarCoder2 LLM
2
12
Sign Extension Bug
2
13
First Instruction Fetch Bug
2
14
RISC-V instruction corpus
2
15
MIPS ISA
2
16
algebraic data type
2
17
many-sorted logic
2
18
CoreIR
2
19
bfloat16
2
20
register dependencies
2
21
RISC-V Foundation
2
22
pipeline interlocks
2
23
vector memory instructions
2
24
CSRRW
2
25
JTAG interface verification
2
26
DMA interface verification
2
27
DII Stream
2
28
RVFI Stream
2
29
Vengine
2
30
Core-UVM environment
2
31
Spike ISS
2
32
Instruction Set Generator (ISG)
2
33
YAML Configuration
2
34
template parameter iterators
2
35
Fetch Interface Monitoring
2
36
equivalence classes of instructions
2
37
Register File Write Port Monitoring
2
38
HDL Code Generation
2
39
Speculative Fetch
2
40
Trace Merging
2
41
Coverage-Guided Testing
2
42
TLB memory management
2
43
AHB-to-Wishbone Adapter
2
44
Test Program Generation for Microprocessors
2
45
Program Counter Monitoring
2
46
Test Program Generation for Memory Management Units of Microprocessors
2
47
Board Support Package
2
48
StarCoder2
2
49
Hazard3
2
50
RPU
2
51
Power9
2
52
Trap handling flow
2
53
tb_csr.v
2
54
tb_csr.vcd
2
55
assembly program test inputs
2
56
sepc CSR
2
57
merged register file
2
58
ISA-Level Instruction Generation
2
59
tag controller
2
60
CHERIvoke
2
61
bounds checking
2
62
instruction pipeline
2
63
capability mode bit
2
64
safe speculation
2
65
Morello
2
66
Memory Protection Unit
2
67
Control Expression (CExpr)
2
68
Data Dependency Analysis
2
69
Exceptions and Interrupts
2
70
Symbolic Binary Simulation
2
71
glitchy_decode
2
72
Machine Learning for Fuzzing
2
73
CompareForContainment Function
2
74
Transistor-Level Verification
2
75
Fault Reporting Issue
2
76
Privilege Levels in RISC-V
2
77
Coverage Bins
2
78
vDSO
2
79
Floating-Point Control and Status Register
2
80
Structural Coverage-Based Fuzzing
2
81
CANbus Protocol
2
82
Dynamic Array
2
83
Conservative Approximation
2
84
Instruction Memory (IMem)
2
85
x86_64 instruction format
2
86
instruction prefix
2
87
cohort output
2
88
worker process ABI
2
89
adversarial instruction sequence
2
90
mishegos worker
2
91
Non-Determinism Removal
2
92
Majority Vote Oracle
2
93
SMV model checker
2
94
regfile_glitches
2
95
Default Data Capability
2
96
principle of least privilege
2
97
software compartmentalization
2
98
Coverage Group Format
2
99
Test Format Spec
2
100
Attributes YAML
2
100 of 4823 shown
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