Data cache miss generation
ConceptData cache miss generation is a cache-testing technique described in the PATARA framework extension for RISC-V-based verification. The available evidence states that PATARA introduces data cache misses by modifying generated data addresses according to the cache line width defined in the target processor description.
First seen 6/1/2026
Last seen 6/1/2026
Evidence 2 chunks
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Data cache miss generation
Data cache miss generation is a test-generation mechanism described for the PATARA self-testing framework. In the cited RISC-V extension work, PATARA was extended with a new approach to generate both instruction-cache and data-cache misses.
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1 connectionsPATARA was extended with a new approach to generate data cache misses.
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[1] PATARA was extended with a new approach to generate instruction and data cache misses. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[2] For the data cache, PATARA modifies data address generation to introduce cache line misses. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[3] Data cache miss generation in PATARA is based on the cache line width specified in the target processor description. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link
[4] Instruction-cache miss testing is described separately as an interleaving sequence using a jump instruction, filler instructions repeated to fill the cache line, and a jump destination. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link