Data cache miss generation

Data cache miss generation is a test-generation mechanism described for the PATARA self-testing framework. In the cited RISC-V extension work, PATARA was extended with a new approach to generate both instruction-cache and data-cache misses.

Mechanism

For the data cache (dcache), the framework modifies data address generation so that generated tests introduce cache line misses. The method is parameterized by the cache line width specified in the target processor description.

Context in PATARA

The dcache miss-generation method appears as part of a broader cache-validation methodology. In the same work, instruction-cache (icache) miss testing is described separately: it is limited to interleaving test sequences, and the miss-provoking sequence consists of a jump instruction, filler instructions repeated to fill the cache line, and a jump destination.

Scope of the available evidence

The provided evidence establishes that PATARA includes a configurable method for generating data cache misses and that the cache line width in the processor description is the relevant configuration input. The evidence does not provide a more detailed low-level algorithm beyond this address-generation-based description.