PATARA

Tool

First seen 5/28/2026

Last seen 6/1/2026

Evidence 9 chunks

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PATARA uses instruction interleaving where modification operations are chained together.

PATARA generates modification operations as part of the REVERSI self-test programs.

PATARA generates restoring operations as part of the REVERSI self-test programs.

PATARA was extended with a new approach to generate data cache misses.

PATARA was extended with a new approach to generate instruction cache misses.

RISC-V core evaluates → 95% 2e

PATARA generates self-test programs to validate the RISC-V core during pre- and post-silicon validation.

PATARA-generated test sequences are also available for pre-silicon verification using FPGA-based rapid prototyping.

PATARA test sequences can be used with FPGA-based rapid prototyping for pre-silicon verification.

The PATARA paper introduces the PATARA open-source tool.

REVERSI extends → 95% 1e

PATARA extends the REVERSI approach with additional features for RISC-V.

REVERSI implements → 100% 1e

PATARA is an open-source tool that implements and extends the REVERSI approach.

focus register uses → 90% 1e

PATARA uses focus register and random register swapping to test data forwarding paths.

PATARA was extended with hardware implementation-dependent pipeline hazard generation mechanisms.

PATARA imports processor and instruction descriptions provided with XML description files.

branch-limiting test introduces → 90% 1e

PATARA introduces the concept of branch-limiting tests for handling conditional branches with limited target address ranges.

PATARA extends pipeline hazard testing to cover data forwarding paths to both source operands.

PATARA is an open-source tool designed for post-silicon validation of processor cores.