branch-limiting test

Concept

In PATARA's RISC-V test-generation extensions, a branch-limiting test is an instruction test whose conditional branch target-range limit constrains how many instructions may be interleaved between its modification and restoring operations. PATARA handles such tests by detecting them in the interleaving stack and splitting long stacks into sub-stacks when the branch-distance limit is reached.

First seen 5/28/2026

Last seen 6/1/2026

Evidence 2 chunks

Wiki v1

WIKI

Definition

In the cited PATARA RISC-V extension work, a branch-limiting test is an instruction test affected by the limited destination target address range of conditional branch instructions, given as ±4 KiB. In these tests, only a limited number of instructions can be placed between the modification operation and the restoring operation.

The paper gives tests such as branch on equal as examples: the conditional branch appears in the modification operation, while the corresponding branch target lies in the restoring operation.

Handling in PATARA

PATARA treats branch-limiting tests as a special case during interleaving. After such a test is detected in the stack of interleaving instructions, the framework counts assembly lines for each following test case. If the branch limit is reached, PATARA splits the stack into two sub-stacks.

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PATARA ← introduces 90% 1e

PATARA introduces the concept of branch-limiting tests for handling conditional branches with limited target address ranges.

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CITATIONS

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5 citations — click to expand

[1] PATARA's RISC-V extension work defines branch-limiting tests as tests constrained by the ±4 KiB destination target address range of conditional branch instructions. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[2] The paper cites tests such as branch on equal as examples, where the conditional branch is in the modification operation and the branch target is in the restoring operation. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[3] When PATARA detects a branch-limiting test in the interleaving stack, it counts assembly lines for subsequent test cases and splits the stack into two sub-stacks once the branch limit is reached. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[4] PATARA executes the first sub-stack normally, passes its result to the second sub-stack, repeats detection and splitting until all instructions are divided into sub-stacks, and thereby supports long interleaved instruction sequences with configurable interleaving length. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link

[5] The branch-limiting-test mechanism is described as the second RISC-V-specific extension implemented in PATARA. A Self-Testing Framework for Verification and Validation of a RISC-V-Based System with a Co-processor | International Journal of Parallel Programming | Springer Nature Link