2026-08-13
2 items 77 entities 98 connections
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
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RISC-V ISA (Instruction Set Architecture) UVM (Universal Verification Methodology) Golden Predictor Model Configuration Layer FlexMem Emulation RTL (Register Transfer Level) ISA Simulator CodAL Instruction-Accurate (IA) Model Cycle-Accurate (CA) Model Design Under Test (DUT) Scoreboard uvm_config_db Ifdef Constructs Functional Coverage Transactors Codasip Ltd. Mentor, A Siemens Business RISC-V Foundation University of California, Berkeley Marcela Zachariášová Luboš Moravec John Stickley Shakeel Jeeawoody Codasip Studio Veloce Emulator Questa RTL Simulator Codix Berkelium Processor SystemVerilog Random Test Generation UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
Processed 44 entities and 54 relations.
Verifying Open Source CPU Cores using Instruction Set Simulators in OVM Environments Waqas Ahmed Siegfried Brandstätter Mario Huemer Royal Institute of Technology (KTH) DMCE GmbH & Co KG Klagenfurt University Open Verification Methodology (OVM) Instruction Set Simulator (ISS) Golden Model Coverage-Driven Constraint Random Verification Functional Verification Formal Verification Register Transfer Level (RTL) Transaction-Level Modeling (TLM) Or1ksim OpenRISC1200 (OR1200) Directed Test Generation Constrained Random Instruction Generation Scoreboard Coverage Model OR1200 Wrapper OR1200 TB Pipeline Synchronization OR1200 Instruction Set ELF Image SystemC FIFO SystemVerilog ModelSim Mentor Graphics Cadence Design System Embecosm Harvard Memory Architecture Multiply-Accumulate (MAC) Unit Arithmetic Logic Unit (ALU) Load/Store Unit (LSU) General Purpose Registers (GPRs) OpenRISC32 C/C++ Compiler Reusable Verification Environment Interface Verification Component (IVC) System Verification Component (SVC) Virtual Sequencer OR1200 Wrapper OR1200 TB