Concept
Concept
4932 entities#
1 word-level tokenization
1 2 Error-Correcting Code
1 3 Cyclic Redundancy Check
1 4 Triple Module Redundancy
1 5 Verification Signoff
1 6 Test Format Specification
1 7 Executable Golden Specification
1 8 Stimulus Constraints
1 9 Test Sequences
1 10 Device Driver
1 11 Bus Interface
1 12 APB
1 13 AHB
1 14 AXI4
1 15 Magic Square Problem
1 16 Map Coloring Problem
1 17 Pipeline Interaction Coverage
1 18 Coverage Point
1 19 Design Tape-Out
1 20 domain reduction
1 21 Architecture Description Language (ADL)
1 22 Temporal Logic Property
1 23 Counterexample-based Test Generation
1 24 Functional Fault
1 25 Set Covering
1 26 Micro-architectural Event
1 27 RACE Solver
1 28 Weighted Distribution
1 29 dcsr.ebreaku
1 30 BDD Solver
1 31 Implication Operator Constraints
1 32 DEC Alpha 21264
1 33 Testcase Extraction Feature
1 34 Linear Temporal Logic (LTL)
1 35 pipeline graph coverage
1 36 cm-gem5c-bin.so
1 37 clock-based counterexample integration
1 38 temporal specification language
1 39 Corner Case Biasing
1 40 deeply pipelined architecture
1 41 FSM model partitioning
1 42 Constraint Answer Set Programming
1 43 event-sequence testing
1 44 CoverageClassLoader
1 45 MutationClassLoader
1 46 SEQ Sequential Reference Model
1 47 Covering Array
1 48 data dependency hazards (RAW, WAR, WAW)
1 49 ASP encoding for optimal strength-2 CMCA finding
1 50 ASP encoding for strength-2 CCT solving with weak coverage constraints
1 51 automated test case generation
1 52 contract-oriented programming
1 53 symbolic animation
1 54 test scenario generation
1 55 branch resolve unit
1 56 type builder
1 57 string builder
1 58 Unordered Floating-Point Reductions
1 59 Step-and-Compare Methodology
1 60 specification language
1 61 vstart
1 62 bounded domain constraint solving
1 63 Speculative Instruction Issue
1 64 Microcode Test Sequence
1 65 control flow vector
1 66 cache coherency violation
1 67 Integer ALU
1 68 wrapper class for sub-class constraint control
1 69 Coherence of Read-Read
1 70 reset_pc
1 71 solution distribution
1 72 memory map
1 73 mret instruction
1 74 two-layer generator architecture
1 75 DRAM region
1 76 IO region
1 77 stimuli packing
1 78 run-and-replace hint
1 79 Cold Start
1 80 Predicate Abstraction
1 81 HTIF
1 82 net.datastructures library
1 83 XML instruction description
1 84 Addressing Modes
1 85 Complex Addressing Modes
1 86 RISC-V A extension
1 87 GShare branch prediction indexing scheme
1 88 RISC-V F extension
1 89 dynamic verification
1 90 Universal Hashing
1 91 A/D bit randomization
1 92 Interval Propagation
1 93 microprocessor architectural state
1 94 PBMT NCIO randomization
1 95 UVM Virtual Sequence
1 96 CPU stimulus configuration JSON
1 97 Pipeline Stages
1 98 illegal instruction execution
1 99 Markov Model based stimulus generation
1 100 mixed Boolean/integer variable domains
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