Concept
Concept
4932 entities#
1 data-independent execution latency
1 2 MP+sync+rs litmus test
1 3 unsafe-custom-hint
1 4 Evolutionary Algorithm
1 5 Mapping Scheme
1 6 Cryptographic Seed for Deterministic Randomness
1 7 delay injection attack
1 8 RISC-V Data-Independent Execution Latency (DIEL) mode
1 9 Structured RISC-V Tokenizer
1 10 AHB Verification IP
1 11 C++ reference model
1 12 UVM Register Abstraction Layer
1 13 Bi-LSTM
1 14 Binary Search-Based Minimization
1 15 RISC-V Toolchain
1 16 GDB Remote Serial Protocol (RSP)
1 17 TestsetCodeErrMinRunner
1 18 GNU RISC-V Toolchain
1 19 digital twin simulation
1 20 CVSS vulnerability scoring
1 21 hardware vulnerability discovery
1 22 Interrupt Agent
1 23 Memory Interface Agent
1 24 IEEE floating point semantics
1 25 non-multicopy-atomic architecture
1 26 litmus tests
1 27 cycle-accurate simulation model
1 28 C/C++11 concurrency
1 29 GDBRunner
1 30 TSO memory model
1 31 SAT/SMT solvers
1 32 Timing Model
1 33 core_integrate.sh
1 34 toolchain_paths.sh
1 35 sim.py
1 36 Just-in-Time Compilation (JIT)
1 37 dcsr.ebreakm
1 38 dynamic taint tracking
1 39 UVM Factory
1 40 Illegal State Transition Identification
1 41 enumerate_transitions_of_system function
1 42 Incremental Constraint Specification
1 43 Executable and Linkable Format (ELF)
1 44 Counterexample Reduction
1 45 RISC-V D extension
1 46 EPEX
1 47 configuration register randomization
1 48 Symbolic Quick Error Detection (SQED)
1 49 RISC-V C extension
1 50 GDB Remote Debug Protocol (RDB)
1 51 configuration register random coverage
1 52 Directed Test Suites
1 53 Resource Reallocation
1 54 randomised testing
1 55 ARMv8 instruction set
1 56 RVFI trace
1 57 cross-entropy loss minimization
1 58 executable simulator
1 59 test shrinking
1 60 microarchitectural mutation coverage
1 61 Sail JAL semantics
1 62 Genetic Algorithm
1 63 RISC-V H extension
1 64 Instruction Sequence State Space
1 65 Cumulative Step-Size Adaptation
1 66 RISC-V V extension
1 67 IPOP Restart Strategy
1 68 BIPOP Restart Strategy
1 69 RISC-V U mode
1 70 Stochastic Superoptimization
1 71 RISC-V S mode
1 72 RAW hazard avoidance constraint
1 73 DII (Direct Instruction Injection)
1 74 Syntax-Guided Synthesis
1 75 AIGER
1 76 SMV
1 77 BTOR2
1 78 Differential Fault Analysis
1 79 FlashFill
1 80 Markov Chain Monte Carlo
1 81 Beam Search
1 82 secure access probability
1 83 State Update Function
1 84 secure page table probability
1 85 Tiny AES
1 86 hardware capabilities
1 87 intellectual property (IP) block
1 88 Rocket Chip SoC Generator
1 89 ECO validation
1 90 Debug Transport Module
1 91 Naturally Aligned Power-of-2 (NAPOT)
1 92 phase analysis
1 93 Naturally Aligned Four-byte (NA4)
1 94 Trace-Guided TCG
1 95 simulation points
1 96 Lock Bit Mechanism
1 97 rv32
1 98 Hardware-Software Interface
1 99 electronic design automation (EDA)
1 100 Parity
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