Concept
Concept
4932 entities#
1 uvm_config_db
2 2 SystemVerilog Coverage Models
2 3 Instruction Set Processor (ISP) Description
2 4 golden reference simulation
2 5 Hypervisor Verification
2 6 Bayesian Network-based Coverage-directed Test Generation
2 7 Instruction-Level Abstraction
2 8 Abstract Interpretation
2 9 Sparse Reward Problem
2 10 VeeRwolf
2 11 Smart Shrinking
2 12 Instruction Set Generator (ISG)
2 13 YAML Configuration
2 14 template parameter iterators
2 15 sampling variables
2 16 Constrained Randomization
2 17 Intrinsic Reward
2 18 SMT-LIB2
2 19 Instruction Mix (IMIX)
2 20 Lockup Bug Detection
2 21 interrupt generation
2 22 Bit Vector
2 23 Hardware Multithreading
2 24 Fetch Interface Monitoring
2 25 equivalence classes of instructions
2 26 Self-Checking Test
2 27 Register File Write Port Monitoring
2 28 blocking clauses
2 29 HDL Code Generation
2 30 Speculative Fetch
2 31 Trace Merging
2 32 Java Constraint Solver API
2 33 PC generation
2 34 RISC-V Compliance Suites
2 35 Structural and Value Coverage Rules
2 36 Coverage-Guided Testing
2 37 Bare-Metal Test Generation
2 38 SMTLib benchmarks
2 39 privileged mode
2 40 TLB memory management
2 41 Return-Oriented Programming
2 42 AHB-to-Wishbone Adapter
2 43 Test Program Generation for Microprocessors
2 44 Program Counter Monitoring
2 45 SIMD instructions
2 46 Test Program Generation for Memory Management Units of Microprocessors
2 47 Micro-architectural Bugs
2 48 Instruction Fetch Interface Monitoring
2 49 Branch Transition Rate (BTR)
2 50 Polymorphism
2 51 CPU-Subsystem UVM environment
2 52 Computer Program Product for Random Loop Test Generation
2 53 RISC-V Timer
2 54 xwr_access Test
2 55 Board Support Package
2 56 Directed Test Bench
2 57 StarCoder2
2 58 Hazard3
2 59 instruction overhead
2 60 bus memcheck
2 61 benchmark workload
2 62 RPU
2 63 HINT instruction generation
2 64 Instruction Group Coverage Points
2 65 Object-Oriented Programming (OOP)
2 66 Architectural Coverage
2 67 Formal Verification Methods
2 68 Power9
2 69 rand_instr_test
2 70 MIPS Instruction Set
2 71 Trap handling flow
2 72 tb_csr.v
2 73 tb_csr.vcd
2 74 assembly program test inputs
2 75 Memory Disambiguation
2 76 Register Type Pool
2 77 AMBA CHI Protocol
2 78 Caliptra Root of Trust
2 79 vector/hypervisor extensions
2 80 Address Matching
2 81 XWR Permissions
2 82 Memory Management
2 83 Processor Pre-Silicon Functional Verification
2 84 Morphing Map
2 85 Branch Misprediction Rate
2 86 sepc CSR
2 87 snapshot debugging
2 88 Race Condition
2 89 ISA checker
2 90 Coverage Masking Effect
2 91 TLB operations
2 92 CSR (Control and Status Register)
2 93 constraint
2 94 Register Reuse
2 95 merged register file
2 96 ISA-Level Instruction Generation
2 97 tag controller
2 98 Weighted Knobs
2 99 Target Address Buffer
2 100 CHERIvoke
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