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STIMSMITH
Concept

Concept

4823 entities
#
1
Genetic Programming
2
2
Single Group Mapping
2
3
Dynamic Bin Mapping
2
4
Bit-flip Fault Effect
2
5
Prefetch Buffer
2
6
Synchronous Digital Circuit
2
7
VCD Waveform Trace
2
8
Laser Fault Injection
2
9
offset applier instruction
2
10
FISSC Benchmark
2
11
Lockstep Core
2
12
Combinational Function
2
13
Register Transition Function
2
14
Depth-First Search
2
15
Selective Testing
2
16
Top of Range (TOR)
2
17
false positive detection
2
18
Load-Reserved Store-Conditional
2
19
Architectural Testing
2
20
ISA Coverage Specification
2
21
Signature-Based Testing
2
22
Data Propagation Analysis
2
23
N-Queens Problem
2
24
CGF Format
2
25
IP Core
2
26
Chain of Thought Prompting
2
27
Program of Thoughts
2
28
Uniform Stimulus Generation
2
29
ISA-level Test Program Generation
2
30
Path Selection in FSM
2
31
Model Context Protocol
2
32
ReAct
2
33
run_loop function
2
34
biased-random test generation
2
35
pipeline interaction fault
2
36
Conjunctive Normal Form
2
37
SAT-based bounded model checking
2
38
processor model decomposition
2
39
functional fault model
2
40
dynamic scheduling
2
41
completion queue
2
42
graph-based functional test program generation
2
43
prioritized combinatorial testing
2
44
Leapfrogging Optimization
2
45
k-Random Mutant Filter
2
46
Combinatorial Testing
2
47
ASP encoding for strength-2 CMCA finding
2
48
Dynamic Memory Allocation
2
49
CLINT
2
50
store buffer
2
51
Sequential Consistency
2
52
landing zone
2
53
load value axiom
2
54
syntactic dependency
2
55
Mu2 Source Code
2
56
coverage-directed generation
2
57
RISC-V instruction sequence generation
2
58
hardware fuzzer IP
2
59
VeeR EL2 Core
2
60
Partial Evaluation
2
61
Instantiation Mode Analysis
2
62
Structural Coverage Criteria
2
63
Java Bytecode
2
64
Random Seeding of SAT Solver
2
65
Weighted Binary Decision Diagram
2
66
coverage criteria
2
67
unbreakable section
2
68
OP-TEE
2
69
cache operations
2
70
direct memory access
2
71
prologue section
2
72
epilogue section
2
73
Custom Instruction Streamer
2
74
Multi-target Coverage Feedback
2
75
Test Case Generator (TCG)
2
76
Coverage Visualization
2
77
mtcfuzz_record_tb_exec
2
78
sampling variables
2
79
Constrained Randomization
2
80
SMT-LIB2
2
81
Bit Vector
2
82
blocking clauses
2
83
SMTLib benchmarks
2
84
xwr_access Test
2
85
Directed Test Bench
2
86
Caliptra Root of Trust
2
87
Address Matching
2
88
XWR Permissions
2
89
Race Condition
2
90
concrete classification level
2
91
abstract classification level
2
92
class classification level
2
93
Silicon Bring-Up
2
94
Write-Write Collision
2
95
Load/Store Instruction Generation
2
96
power state transition
2
97
PCIe interaction
2
98
reset signal
2
99
machine check exception
2
100
speculative memory operation
2
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