Concept
Concept
4932 entities#
1 Kernel Page-Table Isolation
2 2 Page Fault
2 3 knob-based instruction generation
2 4 Context-Sensitive Probabilities
2 5 software-facing verification
2 6 Branch Scenario Generation
2 7 Random Seeding of SAT Solver
2 8 Unconstrained Opcode (Free Stimulus)
2 9 Weighted Binary Decision Diagram
2 10 C Token Categories for Prompt Templates
2 11 Binary File Mutation
2 12 Scenario Generator
2 13 functional coverpoints
2 14 Test Generator Implementation in C
2 15 coverage criteria
2 16 rand_intf class
2 17 MMU Stress Testing
2 18 FPGA-accelerated coverage collection
2 19 Test Suite Minimization
2 20 unbreakable section
2 21 ISA-Level Mutation Classes
2 22 Counterexample-Driven Development
2 23 Transaction-Level Model (TLM)
2 24 Instruction Shuffle
2 25 Instruction Diversity
2 26 Instruction Class Enumeration
2 27 Human-in-the-Loop Triage
2 28 Algorithm 1: Filter for Non-Progressing Testcases
2 29 Algorithm 2: Reachability Analysis for Uncovered Point
2 30 Algorithm 3: LLM-Guided Property Generation
2 31 Taint Analysis
2 32 factory pattern
2 33 Micro-op (micro-operation)
2 34 instr datatype
2 35 valid instruction sequences
2 36 arm_factory
2 37 Qwen LLM Family
2 38 StarCoder2 LLM
2 39 OP-TEE
2 40 simd_factory
2 41 Sign Extension Bug
2 42 First Instruction Fetch Bug
2 43 IDL language
2 44 Instruction Coverage Points
2 45 ASMcoret record
2 46 FPGA-based Verification
2 47 RISC-V instruction corpus
2 48 ELF File Execution
2 49 Hard-to-Test Faults
2 50 instruction FIFO filling
2 51 Bottom-Up Implementation
2 52 Constrained-Random Scenario
2 53 Branch Scenario Verification
2 54 MIPS ISA
2 55 Fault Space
2 56 Functional Test
2 57 algebraic data type
2 58 many-sorted logic
2 59 cache operations
2 60 CoreIR
2 61 direct memory access
2 62 Speculative Fetch Detection
2 63 bfloat16
2 64 ThunderX2
2 65 prologue section
2 66 assertSE primitive
2 67 epilogue section
2 68 digital signal processor
2 69 register dependencies
2 70 RISC-V Foundation
2 71 Invariant
2 72 Simulator-Based Coverage
2 73 Fetch and Commit Trace Merging
2 74 CSP/SMT Solver
2 75 pipeline interlocks
2 76 Speculative Execution Verification
2 77 vector memory instructions
2 78 Illegal Opcode Stimulus
2 79 Custom Instruction Streamer
2 80 Sequence Assertions
2 81 Dual-Core Lockstep (DCLS)
2 82 CSRRW
2 83 Multi-target Coverage Feedback
2 84 JTAG interface verification
2 85 Forwarding Structure Testing
2 86 DMA interface verification
2 87 DII Stream
2 88 Test Case Generator (TCG)
2 89 RVFI Stream
2 90 capability pointer
2 91 Vengine
2 92 Coverage Visualization
2 93 Reorder Buffer Monitoring
2 94 Coordinate List Format (COO)
2 95 Core-UVM environment
2 96 FPU Operations
2 97 mtcfuzz_record_tb_exec
2 98 Spike ISS
2 99 host-FPGA communication overhead
2 100 Randomized Test Strategy
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