bus memcheck

Concept

Bus memcheck refers to a family of formal verification checks within the riscv-formal framework that validate a RISC-V core's behavior on its instruction and data memory buses. The family includes the data bus memcheck, the instruction bus fault memcheck, the data bus fault memcheck, and a set of data bus I/O checks. These bus-level checks supersede the earlier, equivalent instruction memcheck and data memcheck checks.

First seen 6/7/2026

Last seen 6/7/2026

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WIKI

Overview

In the riscv-formal verification framework, a set of checks collectively referred to as bus memcheck validate how a RISC-V core interacts with the memory bus. Each check introduces a small, abstract memory model and observes bus traffic (via the RVFI bus interface) to confirm that the core's retired memory accesses, faults, and I/O behavior are consistent with what appears on the bus.

The bus memcheck checks are part of the broader memory abstraction machinery used by riscv-formal [evidence: 9adf98b4-b25d-4071-b16a-6d418db8e707]. The bus-level checks supersede the earlier, simpler instruction memcheck and data memcheck checks, which are no longer managed by genchecks.py and have been replaced by their standard bus-check equivalents [evidence: 9adf98b4-b25d-4071-b16a-6d418db8e707].

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RELATIONSHIPS

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memory abstraction ← part of 92% 1e

Bus memchecks add a memory abstraction for bus-level verification

instruction memcheck derived from → 90% 1e

The bus memcheck supersedes the older instruction memcheck

data memcheck derived from → 90% 1e

The bus memcheck supersedes the older data memcheck

LINKED ENTITIES

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memory abstraction PART_OF Extracted graph relationship

instruction memcheck DERIVED_FROM Extracted graph relationship

data memcheck DERIVED_FROM Extracted graph relationship

CITATIONS

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10 citations — click to expand

[1] Bus memcheck checks add a memory abstraction that emulates a single word of memory at an unconstrained address, and are part of the broader memory abstraction machinery used by riscv-formal. Verification procedure - RISC-V Formal documentation

[2] The earlier Instruction memcheck and Data memcheck checks are superseded by the equivalent standard bus checks. Verification procedure - RISC-V Formal documentation

[3] The bus_dmem check tests that writes and reads reported via RVFI are consistent with a single read/write word at an unconstrained address, that an initial value as reported via RVFI matches the fetched bus value, and that it does not require writes to appear on the bus, making it cache-compatible. Verification procedure - RISC-V Formal documentation

[4] The RISCV_FORMAL_FAULT_WIDTH macro must be defined when the granularity of access faults as observed from the core is coarser than the width of the bus (e.g., a cache-line granularity). Verification procedure - RISC-V Formal documentation

[5] The bus_imem_fault check adds a single always-faulting word of memory and verifies that executing from that address raises an 'instruction access fault' trap, with RVFI signaling rvfi_trap and an all-zero rvfi_insn. Verification procedure - RISC-V Formal documentation

[6] The bus_dmem_fault check verifies that a read from the faulting address causes a 'load access fault' and a write causes a 'store/AMO access fault', with RVFI signaling rvfi_trap and no register update or memory write. Verification procedure - RISC-V Formal documentation

[7] When RISCV_FORMAL_MEM_FAULT is defined, the bus_imem_fault and bus_dmem_fault checks require the associated fault signals to be set correctly. Verification procedure - RISC-V Formal documentation

[8] The data bus I/O checks (bus_dmem_io_read, bus_dmem_io_read_fault, bus_dmem_io_write, bus_dmem_io_write_fault, bus_dmem_io_order) provide stronger guarantees for I/O memory regions and can be configured for specific addresses via the RISCV_FORMAL_IOADDR(addr) macro. Verification procedure - RISC-V Formal documentation

[9] bus_dmem_io_read requires that every retired non-faulting I/O memory read appears as an individual read in a single RVFI_BUS cycle, and bus_dmem_io_write requires that every non-faulting I/O memory write appears individually in a single RVFI_BUS cycle without writing adjacent bytes. Verification procedure - RISC-V Formal documentation

[10] bus_dmem_io_order checks that every pair of adjacent I/O memory accesses observed via RVFI corresponds to adjacent I/O memory accesses on the bus, ignoring non-I/O accesses. Verification procedure - RISC-V Formal documentation