SystemVerilog Coverage Models
CodeArtifactSystemVerilog Coverage Models are functional coverage artifacts used in RISC-V verification flows to measure exercised ISA features and system behaviors. In the provided evidence, ImperasFC/ImperasSC can auto-generate these models for RISC-V ISA features, and ImperasFC can generate them directly from the ISA specification. Because the models are conventional SystemVerilog, results can be viewed in standard coverage reporting tools such as Verdi and extended by users for custom features and cross-coverage.
WIKI
Overview
SystemVerilog Coverage Models are functional coverage artifacts used in RISC-V verification to measure how thoroughly stimulus exercises ISA features and system behaviors. The evidence describes functional coverage and stimulus coverage as metrics for understanding coverage gaps in RISC-V verification, with automatically generated coverage models providing detailed insight into those gaps. [C1]
Generation
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →