Address Matching

Concept

Address matching is a configuration parameter in RISC-V Physical Memory Protection (PMP) that specifies how region boundaries encoded in `pmpaddrX` Control and Status Registers are interpreted to define physical memory regions. Three modes are defined: Top of Range (TOR), Naturally Aligned Four-byte (NA4), and Naturally Aligned Power-of-2 (NAPOT).

First seen 7/30/2026

Last seen 7/30/2026

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Overview

In the RISC-V Physical Memory Protection (PMP) architecture, address matching refers to the way boundaries of memory regions are calculated from the values stored in the PMP address registers (pmpaddrX). The address matching mode is encoded in bits [4:3] (A field) of the corresponding PMP configuration register (pmpcfgX), and determines how the address in pmpaddrX is interpreted when defining a region boundary.

Address Matching Modes

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RELATIONSHIPS

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Physical Memory Protection (PMP) ← uses 97% 2e

PMP uses address matching to calculate region boundaries

Naturally Aligned Power-of-2 (NAPOT) ← part of 97% 1e

NAPOT is one of three address matching modes in PMP

Naturally Aligned Four-byte (NA4) ← part of 97% 1e

NA4 is one of three address matching modes in PMP

Top of Range (TOR) ← part of 97% 1e

TOR is one of three address matching modes in PMP

LINKED ENTITIES

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Physical Memory Protection (PMP) USES Extracted graph relationship

Naturally Aligned Power-of-2 (NAPOT) PART_OF Extracted graph relationship

Naturally Aligned Four-byte (NA4) PART_OF Extracted graph relationship

Top of Range (TOR) PART_OF Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] Address matching refers to the way boundaries of memory regions are calculated, with three available modes in PMP: NAPOT, NA4, and TOR. Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

[2] In TOR mode, the upper boundary is calculated as pmpaddrX << 2 because the address stored in the address register represents bits [33:2] of the physical address space. Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

[3] For NAPOT, the upper boundary is calculated as 2^(n+3) where n is the number of set least-significant bits in pmpaddrX; the smallest encodable region is a 4-byte range. Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

[4] The address matching configuration (bits 4,3) is read from the PMP CSRs to determine how each pmpaddrX is interpreted during a region match. Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

[5] Once a matching region is found, bits [2:0] of the PMP configuration register decode X/W/R permissions for execution, writes, and reads respectively. Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

[6] In cryptocurrency research, cross-chain address matching identifies when addresses in incompatible formats (e.g., Bitcoin and Ethereum) derive from the same public keys, exposing key reuse. Reuse of Public Keys Across UTXO and Account-Based Cryptocurrencies

[7] In a low-power AI ASIC, local target address matching eliminates the address bus between processor-memory nodes, reducing data transport energy costs. Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator