RISC-V Compliance Suites

Concept

RISC-V compliance suites are directed validation test suites used to provide structured architectural and feature coverage in processor verification flows. In the provided evidence, ImperasTS is the main example: it includes TS-ISA architectural validation tests similar to compliance suites, plus targeted suites for vector, MMU, PMP, and ePMP features. These suites are self-checking, compare results against a reference model, and are used with constrained-random stimulus to close coverage gaps across simulation, emulation, FPGA prototyping, and silicon-oriented validation.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 2 chunks

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WIKI

Overview

RISC-V compliance suites are directed test suites used in RISC-V processor verification to provide structured architectural validation and feature coverage. The evidence describes ImperasTS as a directed suite family that complements constrained-random generation by targeting areas where random stimulus can leave coverage gaps. [C1]

Within this flow, TS-ISA provides architectural validation tests described as similar to compliance suites and included with ImperasDV licences. Additional ImperasTS suites target vector extensions, virtual memory, and protection features. [C2]

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RELATIONSHIPS

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ImperasTS-ISA ← evaluates 93% 1e

ImperasTS-ISA provides architectural validation tests similar to compliance suites, included with ImperasDV licences.

LINKED ENTITIES

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PMP targets_feature PMP is listed as a memory protection feature covered by directed suites.

ePMP targets_feature ePMP is listed with PMP as a protection feature covered by directed suites.

ImperasDV integrates_with The evidence says TS-ISA is included with ImperasDV licences and that ImperasDV enables lock-step comparison against a reference model.

STING complements The evidence describes a hybrid methodology combining constrained-random stimulus from STING with directed ImperasTS suites.

ImperasFC supports_coverage_analysis The evidence says a hybrid workflow uses functional coverage analysis with ImperasFC to identify gaps before applying targeted directed tests.

CITATIONS

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10 citations — click to expand

[1] ImperasTS directed suites complement constrained-random generation by targeting coverage gaps. source

[2] TS-ISA is an architectural validation test suite similar to compliance suites and included with ImperasDV licences; TS-VECT targets vector extensions; TS-MMU, PMP, and ePMP target virtual memory and protection features. source

[3] Vector, MMU, PMP, and ePMP suites are configured to match the user's RISC-V processor, and TS-MMU tests can expose coverage-gap-related issues such as TLB flush ordering problems after Sv39 and Sv48 page-table-walk coverage analysis. source

[4] A hybrid workflow begins with STING constrained-random sweeps, uses ImperasFC functional coverage analysis, and applies targeted directed suites for remaining gaps. source

[5] ImperasTS suites are self-checking and automatically compare results against a reference model to uncover subtle design issues and accelerate coverage closure. source

[6] ImperasDV supports lock-step comparison against a reference model at instruction retirement, and combining self-checking tests with lock-step comparison improves debug efficiency. source

[7] RISC-V test stimulus can be portable across simulation, emulation, FPGA prototyping, and silicon, supporting shift-left verification and reuse from RTL bring-up into later validation stages. source

[8] The described flow can execute constrained-random programs in VCS, use Verdi for centralized debug, and reuse stimulus in ZeBu emulation or HAPS prototyping. source

[9] The hybrid approach provides faster coverage closure, scalability and reproducibility through seeds and reruns, and support for profiles and privilege-related specifications including RVA22, RVA23, MMU, PMP, hypervisor, and vector extensions. source

[10] Recommended next steps include broad STING exploration, applying ImperasTS suites for compliance and feature gaps, integrating coverage and debug with Verdi, replaying failing cases in VCS, and shifting verification earlier with ImperasSC. source