Universal Verification Methodology (UVM)

Overview

The Universal Verification Methodology (UVM) is a standardized verification methodology widely used in industry to verify digital designs through structured and reusable testbenches. Verification remains a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total development effort [arxiv:2605.04704v2]. UVM addresses this by providing a framework that improves reuse and supports constrained-random verification.

UVM is built on SystemVerilog (SV), standardized as IEEE 1800-2017 [chipsalliance.org/news/sv-tools-project-launch/]. The methodology relies on constructs such as verification components, agents, scoreboards, reference models, and constrained-random stimulus generation.

Applications in RISC-V Verification

UVM has been applied extensively to RISC-V processor and system verification. A representative example is the work from the Barcelona Supercomputing Center (BSC) for the Barcelona Zettascale Lab (BZL) project, where a multi-level UVM environment was used to verify a system composed of three RISC-V cores (including in-order Sargantana and out-of-order Lagarto KA/OX cores) and their cache hierarchy [riscv-europe.org/summit/2025/media/proceedings/2025-05-14-RISC-V-Summit-Europe-P2.1.05-GENOVESE-abstract.pdf].

In the BSC environment:

• Core-UVM level: The DUT is the core itself, with agents monitoring complete_if (retired instruction state including PC, destination register, and CSR contents), int_if (interrupt injection and trap detection), dc_if (data cache interface), and ic_if (instruction cache interface). A modified Spike ISS is used as a reference model for co-simulation, with results compared in a scoreboard. The simulation preloads binaries into both memory and Spike, executes the test, and terminates early on scoreboard mismatches, timeouts, or assertion failures.
• CPU-Subsystem UVM level: The DUT is the full system with three cores and three cache levels. It reuses the core-UVM instance in passive mode, adds AXI Slave Memories (modelled using the axi-mem component from the Pulp project), a JTAG VIP, and an AXI Master VIP for DMA verification.

The BSC verification strategy combines UVM environments with randomly generated binaries from the riscv-dv instruction generator (modified to provide full RVV 1.0.0 support and enhanced trap handling) together with directed tests from riscv-tests and compliance suites [riscv-europe.org/summit/2025/media/proceedings/2025-05-14-RISC-V-Summit-Europe-P2.1.05-GENOVESE-abstract.pdf].

UVM in Open-Source Tooling

RISCV-DV (Instruction Generator)

The SV/UVM-based RISCV-DV framework, contributed by Google to CHIPS Alliance, is an instruction generator for RISC-V processors used for verifying features such as privileged modes and trap/interrupt handling. Generated instructions are executed by the core under test and simultaneously by a reference RISC-V ISS (e.g., Spike or Renode), with core states compared after each executed instruction. This co-simulation setup is used in the verification workflows of many RISC-V ecosystem cores, including the CHIPS Alliance VeeR EL2 core and lowRISC's Ibex [chipsalliance.org/news/sv-tools-project-launch/].

UVM in Verilator

Long-running efforts to enable UVM testbenches in Verilator, driven by Antmicro, Wilson Snyder, and other contributors, have produced uvm-verilator. The most recent milestone is support for upstream UVM 2017 in Verilator. Bringing UVM to Verilator (both open source and widely adopted in the industry) is an important step toward a fully open-source ASIC development flow [chipsalliance.org/news/sv-tools-project-launch/].

CHIPS Alliance SV Tools Project

The SV Tools Project, an initiative under CHIPS Alliance (operating under the Linux Foundation), groups together open-source tools for SystemVerilog/UVM-based development: the sv-tests suite (used to benchmark coverage of the SV standard, e.g., tracking milestones such as the addition of UVM support to Verilator), Verible, Synlig, and RISCV-DV [chipsalliance.org/news/sv-tools-project-launch/].

LLM-Assisted UVM Testbench Generation

Recent research has explored using Large Language Models (LLMs) to automate UVM testbench construction, addressing the manual coding burden and need for domain expertise. Two notable frameworks include:

• UVM^2: Generates UVM testbenches and iteratively refines them using coverage feedback, reducing testbench setup time significantly compared to experienced engineers while achieving average code coverage of 87.44% and function coverage of 89.58% [arxiv:2504.19959v4].
• UVMarvel: An automated framework for subsystem-level RTL verification across mainstream bus protocols. It introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and uses a Signal Tracker and Verilog Patching Library to guide LLM-based stimulus refinement. UVMarvel achieves an average code coverage of 95.65% and reduces verification time from several human working days to a 4.5-hour automated execution [arxiv:2605.04704v2].

Cross-References

• Verilator: Open-source RTL simulator that implements UVM support via uvm-verilator.
• RISCV-DV: SV/UVM-based instruction generator that implements UVM-style verification for RISC-V processors.
• uvm-verilator: Code artifact providing UVM testbench support in Verilator.
• Spike: RISC-V Instruction Set Simulator used as a reference model in UVM co-simulation environments.
• riscv-tests: Directed test suite commonly combined with UVM environments for compliance testing.
• Ibex: lowRISC RISC-V core whose verification workflow uses RISCV-DV/UVM.
• VeeR: CHIPS Alliance RISC-V CPU core verified using RISCV-DV/UVM.