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STIMSMITH
Concept

Concept

4823 entities
#
1
Application-Set Driven Architecture Exploration
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2
VerifRoCCStandalone.scala
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3
clock-based counterexample integration
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4
Bank Conflict
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5
temporal specification language
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6
SiFive U74 CPU
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7
Genetic Algorithm-Based Test Generation
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8
CHERI Concentrate Compression
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9
deeply pipelined architecture
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10
Reduction Reference Model in C
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11
FSM model partitioning
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12
Error Modelling
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13
TLB Flush Logic
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14
Constraint Answer Set Programming
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15
event-sequence testing
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16
arc-consistency
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bare metal test harness
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18
CoverageClassLoader
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19
MutationClassLoader
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20
Coarse-Grained Reconfigurable Architecture
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Subgraph Isomorphism
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Covering Array
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Dynamic Programming
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24
Microcode Test Sequences
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25
custom opcode space (custom-0 through custom-3)
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26
ELF Format
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mret instruction
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28
SweRV (VeeR EL2)
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29
CVA6 (Ariane)
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30
Bayesian Network-Based Test Generation
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Zenbleed
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Machine Learning-Based Test Generation
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OtherIllegal Instruction Category
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stimuli packing
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35
SiliFuzz
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Verilator
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37
RISCover Artifacts Repository
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38
memory operation retry
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39
Predicate Abstraction
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40
Microcode Update
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41
net.datastructures library
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42
LLM
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43
Birgus-variant
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ACT4 framework
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45
Addressing Modes
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Complex Addressing Modes
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Reconfigurable Processor
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Application Scheduling
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Runtime Reconfigurable Cells
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Processor Extensions
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dynamic verification
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Universal Hashing
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Lazy Memory Mapping
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Interval Propagation
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Privileged CSR Randomization
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MIPS-CPU
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input minimization
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passes.yml
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RISC ISA
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PCIe
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analysis filter
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analysis pass
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Single Event Upset (SET)
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shared memory slot
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window-based fuzzing
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CVE-2024-44067
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SIB byte
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ModR/M byte
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instruction candidate generation
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None Instruction Category
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variable-length instruction encoding
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solution uniformity
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constraint-based sampling
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rejection sampling
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uniform sampling
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pre_randomize and post_randomize callbacks
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set_RTR task
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getbits task
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randomize() method
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binary decision diagrams
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Trusted Firmware-A
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Detectable Unrecoverable Error (DUE)
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CPU-initiated memory access
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external stimulus
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JSON program representation
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message_t struct
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inter-scenario event
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User Constraints File
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Microprocessor Architecture Modeling
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90
flip-flop-level fault injection
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91
DPLL SAT solver
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Sv39 Paging Mode
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Fault Outcome Prediction (FOP)
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Structured Tokenizer
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95
Illegal Bins
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96
Huge Domain Constraint Variables
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Transition Coverage
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Virtual Address Handling Bug
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99
Instruction Prevalence
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100
Symbolic Model Checking
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