Concept
Concept
4932 entities#
1 ASIC
2 2 RISC-V FP extensions
2 3 ROM
2 4 conditional compilation
2 5 Input Stimuli Generation
2 6 projection
2 7 concrete state
2 8 register bypassing
2 9 test situations
2 10 system-call abstraction
2 11 test action
2 12 abstract state
2 13 emu
2 14 formal processor model
2 15 Magic Instruction
2 16 MINRES The Good Core (TGC)
2 17 Hardware Behavior Coverage
2 18 RV64G extension
2 19 Coverage-Directed Test Selection
2 20 Bayesian Network Coverage-directed Test Generation
2 21 rom_aleatoria module
2 22 Device Under Verification
2 23 CRV Strategy
2 24 Automatic Constraint Generation
2 25 covergroups_RISCV class
2 26 Pseudo Memory Unit
2 27 Symbolic Data Memory
2 28 LAVA-M
1 29 Directed Instruction Test
1 30 afl-cmin
1 31 Unified HW/SW coverage
1 32 VAMP SML executable model
1 33 Assumption-Based Bug Workaround
1 34 executable specification
1 35 ConfigGen_AccessControl
1 36 Read-Modify-Write Memory Operation
1 37 DeepSeek LLM Family
1 38 Llama LLM Family
1 39 data-level parallelism
1 40 InputGen_TLUL
1 41 Compressed Instruction
1 42 saturation flag
1 43 architectural validation
1 44 TL-UL
1 45 Skolemization
1 46 atomic instructions stress tests
1 47 RISC-V processor
1 48 Sargantana
1 49 exists-forall formula
1 50 RTL
1 51 On-chip memory
1 52 Agile Hardware Project
1 53 bindSE operator
1 54 8-bit ALU
1 55 cycle-accurate models
1 56 combinatorial model-based generation
1 57 JALR Instruction Bug
1 58 register randomization
1 59 Lagarto KA
1 60 Lagarto OX
1 61 CSRRS
1 62 exception and trap handlers
1 63 RVV 1.0.0 vector instructions
1 64 FPGA Acceleration for Verification
1 65 bootrom preloading
1 66 Wishbone-to-Pipelined-Wishbone Adapter
1 67 Spectre/Microarchitectural Side Channel
1 68 Sargantana
1 69 Lagarto KA
1 70 Lagarto OX
1 71 Barcelona Supercomputing Center
1 72 Branch History Table Verification
1 73 Microcode Verification
1 74 Functional Qualification
1 75 Mutation Adequacy
1 76 Memory Agent
1 77 RVFI Agent
1 78 Assembly File Compilation
1 79 RISC-V Compressed Instructions
1 80 uvm_object
1 81 RVVI-VVP (Virtual Verification Peripherals)
1 82 trace log
1 83 SVA assertions
1 84 Memory Write Monitoring
1 85 Read-Modify-Write
1 86 Generation Directive
1 87 Peephole Superoptimization
1 88 Pipelined Wishbone Adapter
1 89 Verilog Abstract Syntax Tree
1 90 Jaccard Similarity Coefficient
1 91 Processor Pipeline Forwarding Logic
1 92 CSR-Transition Coverage Metric
1 93 Addressing Mode (SAM24/SAM31/SAM64)
1 94 Advanced High-performance Bus (AHB)
1 95 corev_asm_program_gen.sv
1 96 riscv_gen_program_header::gen_program_header()
1 97 Qwen2.5 LLM
1 98 AUK-V-Aethia
1 99 Fedar F1
1 100 Risco-5
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