MINRES The Good Core (TGC)

CodeArtifact

First seen 6/2/2026

Last seen 6/2/2026

Evidence 3 chunks

NEIGHBORHOOD

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4 connections

The paper evaluates the approach using the MINRES TGC 32-bit pipelined RISC-V core as DUT.

RISC-V ISA implements → 100% 2e

MINRES TGC is a 32-bit pipelined RISC-V processor implementing the RISC-V ISA.

MINRES Technologies GmbH authored by → 95% 1e

MINRES TGC is a product of MINRES Technologies GmbH.

Pipeline Verification implements → 85% 1e

MINRES TGC is a pipelined RTL core requiring pipeline-aware verification.