Concept
Concept
4823 entities#
1 EBreakExc Instruction Category
1 2 XML instruction description
1 3 Architectural Compliance Testing
1 4 GShare branch prediction indexing scheme
1 5 Power Management Verification
1 6 microprocessor architectural state
1 7 ARMv6-M
1 8 UVM Virtual Sequence
1 9 performance counter
1 10 SystemC Bus Interfacing
1 11 Function Call Tree
1 12 cpu::step()
1 13 Software-Exploitable Vulnerabilities
1 14 Debug Log
1 15 Processor Security
1 16 CSRRC
1 17 ECALL
1 18 Pipeline Stages
1 19 Misaligned address exception
1 20 Compliance Assurance
1 21 ECall Instruction Category
1 22 assembly listing
1 23 program size parameter
1 24 opcode distribution and biasing
1 25 Markov Model based stimulus generation
1 26 breadth-first search
1 27 mixed Boolean/integer variable domains
1 28 MRet Instruction Category
1 29 Type Variable
1 30 Control Logic
1 31 BMC Completeness Threshold
1 32 Data Path
1 33 DRet Instruction Category
1 34 Constant Value Propagation
1 35 sub-program generation
1 36 UVM Factory Override
1 37 int3
1 38 Program Generation
1 39 ARA Vector Processor
1 40 WFI Instruction Category
1 41 Functional verification of microprocessors
1 42 hybrid quick error detection
1 43 Absolute addressing
1 44 Position-independent code (PIC)
1 45 Return (ret)
1 46 Fence Instruction Category
1 47 Formal model of PowerPC architecture
1 48 Heuristic database of testing expertise
1 49 FenceI Instruction Category
1 50 Bitfield Type
1 51 Compare Point Matching
1 52 Effect System
1 53 Post-Production Test
1 54 Turing-Complete Program
1 55 cov.py
1 56 push_gpr_to_kernel_stack
1 57 riscv_load_store_instr_lib.sv
1 58 OpenRISC Mor1kx Cappuccino
1 59 RISC-V Rocket Core
1 60 RISC-V BOOM Core
1 61 riscv_instr_cover_group.sv
1 62 iss_wrapper
1 63 epac2-vpu-dv
1 64 RAW/WAW/WAR Hazards
1 65 VL (Vector Length)
1 66 Completion Refinement
1 67 riscv_instr_gen_config.sv
1 68 Struct Type
1 69 Interpolant-based Approach
1 70 random branch instruction generation
1 71 SFT training dataset
1 72 SEW (Standard Element Width)
1 73 AXI CHI Protocol
1 74 writeback
1 75 load instruction encoding
1 76 memory region configuration
1 77 Enum Type
1 78 virtual address translation
1 79 LTL Property
1 80 Register Coverage Metric
1 81 VEX Intermediate Representation
1 82 Azuma-Hoeffding Inequality
1 83 Doob Martingale Analysis
1 84 gen_csr_test.py
1 85 configuration instructions
1 86 Overapproximated Machine Instruction Model
1 87 Variable-Length Instruction Architecture
1 88 Decoding Discrepancy
1 89 Hardware Testbench
1 90 x86-64
1 91 Union Type
1 92 Overload Definition
1 93 interrupt delegation vulnerability
1 94 MMU stress test
1 95 Directed Verification
1 96 Instantiation
1 97 Stashing
1 98 Backdoor Access
1 99 Scattered Definition
1 100 Front Door Access
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