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STIMSMITH
Concept

Concept

4932 entities
#
1
blackbox register file
1
2
blackbox ALU
1
3
word-aligned memory access
1
4
Physical Memory Attributes (PMA)
1
5
WFI instruction
1
6
microarchitectural snapshot
1
7
Potential Direct Leakage Channel
1
8
umwait instruction
1
9
Co-Simulation Harness
1
10
Multi-Hart Design
1
11
CWE-1342
1
12
register rename stage
1
13
maptable rollback
1
14
CSR register
1
15
umonitor instruction
1
16
Reduction Reference Model in C
1
17
static information flow tracking
1
18
TLB Flush Logic
1
19
Metric-driven Verification
1
20
Forward Tracing
1
21
CV32E40X
1
22
arc-consistency
1
23
Triple Modular Redundancy
1
24
XOR-Gate Fault Injection
1
25
Fault Controller Module
1
26
Random Fault Injection
1
27
Fault Coverage
1
28
Hardware Description Languages
1
29
Fault Tree Analysis
1
30
Runtime Verification
1
31
Double Event Upset
1
32
bare metal test harness
1
33
Microcode Test Sequences
1
34
custom opcode space (custom-0 through custom-3)
1
35
RACE Constraint Solver
1
36
combinatorial coverage
1
37
Hierarchical Configuration
1
38
Moore's Law
1
39
Dennard's Scaling
1
40
ALU Instruction Category
1
41
associative array
1
42
clocking block
1
43
zero delay synchronization
1
44
interface
1
45
modport
1
46
package
1
47
stimuli constraints
1
48
instruction injector
1
49
coverage corpus
1
50
synthesizable coverpoints
1
51
differential checking
1
52
RV64I extension
1
53
R-format instruction
1
54
Retirement-Level Checking
1
55
memory operation retry
1
56
utilidades_verificacion package
1
57
manually generated C and Assembly programs
1
58
Protocol VIP
1
59
Open Bus
1
60
Mul Instruction Category
1
61
rvformal_rand_const_reg
1
62
LLM
1
63
Feedback-Based Verification
1
64
rom_aleatoria_tb module
1
65
SAT solver
1
66
Reinforcement Learning for hardware fuzzing
1
67
top_duv module
1
68
instruction_box typedef
1
69
Div Instruction Category
1
70
Zynq Farm
1
71
U-mode
1
72
rvfi_macros.vh
1
73
assume_stmts.vh
1
74
rvformal_rand_reg
1
75
Mutation Operator
1
76
ACT4 framework
1
77
Crossover Operator
1
78
pwrmgr_env_pkg
1
79
Privileged CSR Randomization
1
80
MIPS-CPU
1
81
DUT (Design Under Test)
1
82
Emulation and FPGA Prototyping
1
83
tb.sv
1
84
pwrmgr.sv
1
85
pwrmgr_wakeup_vseq
1
86
pwrmgr_reset_vseq
1
87
pwrmgr_wakeup_reset_vseq
1
88
Data-Driven Testing
1
89
pwrmgr_lowpower_wakeup_race_vseq
1
90
Functional Coverage Model
1
91
Test Plan Development
1
92
Tracer API
1
93
RISC-V Compliance Tests
1
94
RISC-V RV32I
1
95
Branch Instruction Category
1
96
RTL Mutation Engine
1
97
is_ASMcore predicate
1
98
pwrmgr_bind.sv
1
99
tlul_assert
1
100
clkmgr_pwrmgr_sva_if
1
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