blackbox ALU

Concept

In the riscv-formal verification framework, the 'blackbox ALU' feature (controlled by the `RISCV_FORMAL_BLACKBOX_ALU` macro) allows the actual ALU operations of a core under test to be abstracted away when checking the consistency of the stream of retired instructions (e.g., the 'regcheck' check), so that the formal tool does not need to reason about ALU internals to validate instruction-stream behavior.

First seen 8/1/2026

Last seen 8/1/2026

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WIKI

Overview

blackbox ALU is a configuration option of the riscv-formal framework. It instructs the formal verification environment to hide (black-box) the arithmetic logic unit of the processor core under test when the goal of the check is to verify properties about the stream of retired instructions rather than the exact arithmetic results.

This is useful because reasoning about concrete ALU behavior can be a major source of complexity for the solver. By black-boxing the ALU, the formal engine only needs to establish consistency properties (for example, that retired instructions agree with the register file state) without having to prove the correctness of the ALU's internal computations.

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riscv-formal ← uses 92% 1e

riscv-formal supports black-boxing the ALU during consistency checks.

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CITATIONS

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[1] The `blackbox ALU` option causes the macro `RISCV_FORMAL_BLACKBOX_ALU` to be defined, and is toggled by the presence or absence of the `blackbox` configuration option in riscv-formal. Defining macros - RISC-V Formal documentation

[2] `RISCV_FORMAL_BLACKBOX_ALU` is intended for checks that verify the consistency of the stream of retired instructions, such as the `regcheck` check, not for proving concrete ALU results. Defining macros - RISC-V Formal documentation

[3] `RISCV_FORMAL_BLACKBOX_ALU` may be used inside the core under test to black-box the ALU, complementing `RISCV_FORMAL_BLACKBOX_REGS` which black-boxes the register file for `insncheck`. Defining macros - RISC-V Formal documentation