Reduction Reference Model in C

CodeArtifact

A C reference model used in RISC-V vector accelerator verification to handle unordered floating-point reductions. It implements the same reduction algorithm as the DUT so VPU results can be checked without relying on Spike when Spike’s permitted reduction behavior would otherwise create false mismatches or divergent architectural state.

First seen 5/27/2026

Last seen 6/1/2026

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Overview

The Reduction Reference Model in C is an independent C reference model created for unordered reductions in a RISC-V Vector verification environment. Its purpose is to validate unordered floating-point reduction results when Spike may legally produce a different result due to the rounding mode and reduction algorithm it uses. [C1]

Motivation

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RELATIONSHIPS

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Functional Verification of a RISC-V Vector Accelerator ← uses 98% 1e

A C-based reduction reference model is developed to handle unordered floating-point reductions

Reference Model implements → 97% 1e

The C reduction reference model implements a reference model for unordered reductions

UVM scoreboard ← uses 97% 1e

For unordered floating-point reductions, the UVM scoreboard uses an independent C reference model instead of Spike.

unordered floating-point reduction reference model implements → 99% 1e

The C artifact implements the unordered floating-point reduction reference model matching the DUT algorithm.

LINKED ENTITIES

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Functional Verification of a RISC-V Vector Accelerator USES Extracted graph relationship

Reference Model IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] Spike could produce false mismatches for unordered floating-point reductions, and retained divergent vector-register values could cause later mismatches. Functional Verification of a RISC-V Vector Accelerator

[2] The Reduction Reference Model in C is an independent reference model for unordered reductions and implements the same exact reduction algorithm as the DUT. Functional Verification of a RISC-V Vector Accelerator

[3] For unordered reduction cases, the VPU result is compared against the C reduction reference model instead of Spike, and matching results are injected into Spike registers. Functional Verification of a RISC-V Vector Accelerator

[4] The verification environment included a function to force reduction results into Spike to avoid execution divergence in unordered floating-point reductions. Functional Verification of a RISC-V Vector Accelerator