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Reduction Reference Model in C

CodeArtifact WIKI v1 · 5/27/2026

A C reference model used in RISC-V vector accelerator verification to handle unordered floating-point reductions. It implements the same reduction algorithm as the DUT so VPU results can be checked without relying on Spike when Spike’s permitted reduction behavior would otherwise create false mismatches or divergent architectural state.

Overview

The Reduction Reference Model in C is an independent C reference model created for unordered reductions in a RISC-V Vector verification environment. Its purpose is to validate unordered floating-point reduction results when Spike may legally produce a different result due to the rounding mode and reduction algorithm it uses. [C1]

Motivation

Unordered floating-point reductions created two verification problems when compared directly against Spike:

  1. False mismatches: Spike could produce a result that differed from the DUT even when the DUT result was correct under the RISC-V Vector specification, because the exact unordered reduction behavior can depend on the rounding mode and algorithm used. [C1]
  2. State divergence: Even after recognizing a mismatch as a false positive, the incorrect-for-the-DUT value remained in Spike’s vector registers. Later instructions could consume those values and cause additional mismatches. [C1]

Implementation role

To address this, the verification environment uses an independent reference model written in C for unordered reductions. The model implements the same exact reduction algorithm as the DUT. [C2]

Verification flow

For affected unordered reductions, the VPU result is compared against the C reduction reference model rather than Spike. If the VPU result matches the reduction reference model, that value is injected into Spike’s vector register state so subsequent instructions do not diverge from the DUT state. [C3]

Integration context

The surrounding verification system also included a function to force reduction results into Spike, specifically to avoid execution divergence in unordered floating-point reductions. This complements the C reduction reference model by keeping Spike state aligned after accepting the DUT/model result. [C4]

Related entities

LINKED ENTITIES

2 links
Functional Verification of a RISC-V Vector Accelerator USES
Reference Model IMPLEMENTS

CITATIONS

4 sources
4 citations
[1] Spike could produce false mismatches for unordered floating-point reductions, and retained divergent vector-register values could cause later mismatches. Functional Verification of a RISC-V Vector Accelerator
[2] The Reduction Reference Model in C is an independent reference model for unordered reductions and implements the same exact reduction algorithm as the DUT. Functional Verification of a RISC-V Vector Accelerator
[3] For unordered reduction cases, the VPU result is compared against the C reduction reference model instead of Spike, and matching results are injected into Spike registers. Functional Verification of a RISC-V Vector Accelerator
[4] The verification environment included a function to force reduction results into Spike to avoid execution divergence in unordered floating-point reductions. Functional Verification of a RISC-V Vector Accelerator