Dennard's Scaling

Concept

Dennard's Scaling is presented in the evidence as the historical trend under which CPU frequency and performance grew exponentially until about 2005, benefiting hardware verification by making simulations faster as processor performance improved. After 2005, its impact waned, pushing software toward multicore concurrency and high-performance computing approaches.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

In the cited DVCon paper on accelerating RISCV-DV, Dennard's Scaling is described as the trend that enabled CPU frequency and performance to grow exponentially until around 2005. During this period, verification engineers benefited because increasing hardware-design complexity, associated in the paper with Moore's Law, was offset by corresponding increases in CPU frequency and performance. This made simulation runs proportionately faster as processors improved.^[1]

Role in verification performance

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RELATIONSHIPS

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RISC-V mentions → 70% 1e

The paper mentions Dennard's Scaling in the context of the era before HPC became necessary for RISC-V verification.

CITATIONS

5 sources

5 citations — click to expand

[1] Dennard's Scaling enabled CPU frequency and performance to grow exponentially until around 2005. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x

[2] During the period when Dennard's Scaling held, verification engineers benefited because increased hardware complexity was offset by increased CPU frequency and performance, making simulations proportionately faster. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x

[3] After 2005, the impact of Dennard's Scaling began to wane, and software developers could no longer rely on increased processor frequency to improve software performance. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x

[4] The waning of Dennard's Scaling is linked in the evidence to a shift toward multicore-enabled concurrent programming and the era of High Performance Computing. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x

[5] The cited discussion of Dennard's Scaling appears in the context of RISCV-DV verification performance, where the original SV/UVM implementation is described as generating about 10,000 instructions per second. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x