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Dennard's Scaling

Concept WIKI v1 · 5/26/2026

Dennard's Scaling is presented in the evidence as the historical trend under which CPU frequency and performance grew exponentially until about 2005, benefiting hardware verification by making simulations faster as processor performance improved. After 2005, its impact waned, pushing software toward multicore concurrency and high-performance computing approaches.

Overview

In the cited DVCon paper on accelerating RISCV-DV, Dennard's Scaling is described as the trend that enabled CPU frequency and performance to grow exponentially until around 2005. During this period, verification engineers benefited because increasing hardware-design complexity, associated in the paper with Moore's Law, was offset by corresponding increases in CPU frequency and performance. This made simulation runs proportionately faster as processors improved.[1]

Role in verification performance

The paper frames Dennard's Scaling as a "boon" for verification engineers. As hardware designs became more complex, higher CPU frequency and performance helped compensate by improving simulation throughput. In this account, the scaling trend reduced the practical performance pressure on verification workflows during the period when it held.[1]

End of the "free lunch"

The same source states that Dennard's Scaling continued to dominate until 2005, after which its impact began to wane. The paper connects this transition to Herb Sutter's 2005 paper, "The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software", and states that software developers could no longer rely on rising processor frequency to improve software effectiveness. Instead, programmers needed to write multicore-enabled concurrent programs to improve performance, marking the start of what the paper calls the era of High Performance Computing (HPC).[2]

Context in the cited paper

The discussion appears in a paper about improving UVM testbench performance for RISCV-DV. The paper argues that processor verification can require extremely large numbers of constrained-random instructions, while the original SystemVerilog/UVM RISCV-DV implementation generated about 10,000 instructions per second. Against this backdrop, the decline of Dennard's Scaling motivates multicore and HPC-style approaches to verification-tool performance.[3]

[1]: DVCon paper, chunk 48f37902-9851-450b-8c98-e78ab4a5a7a6. [2]: DVCon paper, chunk 48f37902-9851-450b-8c98-e78ab4a5a7a6. [3]: DVCon paper, chunk 48f37902-9851-450b-8c98-e78ab4a5a7a6.

CITATIONS

5 sources
5 citations
[1] Dennard's Scaling enabled CPU frequency and performance to grow exponentially until around 2005. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x
[2] During the period when Dennard's Scaling held, verification engineers benefited because increased hardware complexity was offset by increased CPU frequency and performance, making simulations proportionately faster. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x
[3] After 2005, the impact of Dennard's Scaling began to wane, and software developers could no longer rely on increased processor frequency to improve software performance. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x
[4] The waning of Dennard's Scaling is linked in the evidence to a shift toward multicore-enabled concurrent programming and the era of High Performance Computing. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x
[5] The cited discussion of Dennard's Scaling appears in the context of RISCV-DV verification performance, where the original SV/UVM implementation is described as generating about 10,000 instructions per second. Crafting a Million Instructions/Sec RISCV-DV: HPC Techniques to Boost UVM Testbench Performance by Over 100x