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Constraint Satisfaction for Test Program Generation

Technique WIKI v1 · 8/1/2026

A test generation technique, introduced by Fournier, Lewin, Levinger, Roytman, and Shurek at the 1995 IEEE International Phoenix Conference on Computers and Communications, that uses constraint satisfaction to automate the creation of test programs for verifying processor designs as part of dynamic, simulation-based functional verification.

Constraint Satisfaction for Test Program Generation

Overview

Constraint Satisfaction for Test Program Generation is a technique for automating the production of test programs used in the functional verification of processor designs. It was introduced in the paper:

L. Fournier, D. Lewin, M. Levinger, E. Roytman, G. Shurek, Constraint Satisfaction for Test Program Generation, IEEE International Phoenix Conference on Computers and Communications, 1995.

The technique treats the construction of a valid and verification-meaningful test program as a constraint satisfaction problem, allowing a generator to systematically combine instruction sequences, operand values, and architectural state so that the resulting program exercises targeted design behavior.

Role in Functional Verification

Functional verification is widely recognized as a major bottleneck in hardware design, with the cited background material noting that up to 70% of development time and resources can be devoted to it. In current industrial practice, dynamic verification dominates: random test generators emit large numbers of tests, each test is simulated on the design-under-verification, and a checker determines whether the simulated behavior matches specification.

Within this paradigm, constraint-based test program generation sits alongside other template- and model-based generators as one of the techniques used to bias and structure randomized tests so that they reach specific "interesting" subspaces of the design's behavior. It is cited as a representative test generator in the same lineage as:

  • Model-Based Test Generation For Processor Design Verification (Lichtenstein, Malka, Aharon, IAAI 1994)
  • Test Program Generation for Functional Verification of PowerPC Processors in IBM (Aharon et al., 32nd DAC, 1995)

Related Approaches and Context

The technique belongs to a broader family of constraint- and graph-based approaches to processor verification that emerged in the early-to-mid 1990s, including:

  • Symbolic Model Checking (McMillan, 1993) and the SMV system (McMillan, 1992).
  • Architectural verification using Symbolic Instruction Graphs (Chandra, Iyengar, Jawalekar, Mullen, Nair, Rosen, ICCD 1994).
  • Constraint solving for test case generation (Chandra, Iyengar, ICCD-92, 1992).
  • Automatic test program generation for pipelined processors (Iwashita, Kowatari, Nakata, Hirose, ICCAD 1994).
  • Architecture validation for processors (Ho, Han Yang, Horowitz, Dill, ISCA 1995).
  • A methodology for processor implementation verification.

These works, together with foundational software-testing theory on partition strategies and revealing subdomains (Weyuker & Jeng, 1991; Weyuker & Ostrand, 1980) and protocol design and validation methodology (Holtzman, 1991), provide the conceptual backdrop against which constraint-satisfaction test program generation was developed.

Summary

Constraint Satisfaction for Test Program Generation operationalizes the idea that the problem of building a useful verification test can be expressed declaratively as a set of constraints over instructions, operands, and architectural state. A solver then produces concrete test programs that satisfy those constraints, providing a structured way to steer dynamic verification toward design subspaces that would be reached only rarely by unstructured random generation.

LINKED ENTITIES

6 links
Constraint satisfaction for test program generation INTRODUCES
Test Program Generation for Functional Verification of PowerPC Processors in IBM RELATED_TO
Model-Based Test Generation For Processor Design Verification RELATED_TO
Architectural Verification of Processors Using Symbolic Instruction Graphs RELATED_TO
Automatic Test Program Generation for Pipelined Processors RELATED_TO
Architecture Validation for Processors RELATED_TO

CITATIONS

5 sources
5 citations
[1] The technique was introduced by L. Fournier, D. Lewin, M. Levinger, E. Roytman, and G. Shurek in the paper 'Constraint Satisfaction for Test Program Generation' at the IEEE International Phoenix Conference on Computers and Communications in 1995. A methodology for processor implementation verification | Springer Nature Link
[2] The paper is cited as a representative test generator alongside other test-generation approaches used to create test cases for verifying combinations of functions in hardware or software designs. US7627843B2 - Dynamically interleaving randomly generated test cases
[3] Functional verification is a major bottleneck in hardware design, with up to 70% of development time and resources typically spent on it, and dynamic verification via randomized test generation and simulation is the dominant industrial practice. US7627843B2 - Dynamically interleaving randomly generated test cases
[4] The technique is co-cited with Model-Based Test Generation For Processor Design Verification (Lichtenstein, Malka, Aharon, IAAI 1994) and Test Program Generation for Functional Verification of PowerPC Processors in IBM (Aharon et al., 32nd DAC, 1995) as test generators used in processor design verification. US7627843B2 - Dynamically interleaving randomly generated test cases
[5] The technique belongs to a 1990s lineage of constraint- and graph-based processor verification approaches including Symbolic Model Checking (McMillan, 1993), the SMV System (McMillan, 1992), Symbolic Instruction Graphs (Chandra et al., 1994), Constraint Solving for Test Case Generation (Chandra & Iyengar, 1992), Automatic Test Program Generation for Pipelined Processors (Iwashita et al., 1994), and Architecture Validation for Processors (Ho et al., 1995). A methodology for processor implementation verification | Springer Nature Link