Constraint Satisfaction for Test Program Generation
TechniqueA test generation technique, introduced by Fournier, Lewin, Levinger, Roytman, and Shurek at the 1995 IEEE International Phoenix Conference on Computers and Communications, that uses constraint satisfaction to automate the creation of test programs for verifying processor designs as part of dynamic, simulation-based functional verification.
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Constraint Satisfaction for Test Program Generation
Overview
Constraint Satisfaction for Test Program Generation is a technique for automating the production of test programs used in the functional verification of processor designs. It was introduced in the paper:
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2 connectionsThe paper introduces the constraint satisfaction technique for test program generation.
Constraint satisfaction for test program generation is a technique used by test generators.
LINKED ENTITIES
6 linksConstraint satisfaction for test program generation INTRODUCES Extracted graph relationship
Test Program Generation for Functional Verification of PowerPC Processors in IBM RELATED_TO Grouped with Constraint Satisfaction for Test Program Generation as a representative test generator used in IBM's processor verification flow.
Model-Based Test Generation For Processor Design Verification RELATED_TO Co-listed with the technique as a test-generation method employed in processor design verification practice.
Architectural Verification of Processors Using Symbolic Instruction Graphs RELATED_TO Shares the early-1990s constraint/symbolic approach to processor verification that motivates constraint-based test program generation.
Automatic Test Program Generation for Pipelined Processors RELATED_TO Another automatic test-program-generation technique from the same era for verifying pipelined processors.
Architecture Validation for Processors RELATED_TO Concurrent processor validation work using formal/symbolic techniques that complements constraint-based test program generation.
CITATIONS
5 sources5 citations — click to expand
[1] The technique was introduced by L. Fournier, D. Lewin, M. Levinger, E. Roytman, and G. Shurek in the paper 'Constraint Satisfaction for Test Program Generation' at the IEEE International Phoenix Conference on Computers and Communications in 1995. A methodology for processor implementation verification | Springer Nature Link
[2] The paper is cited as a representative test generator alongside other test-generation approaches used to create test cases for verifying combinations of functions in hardware or software designs. US7627843B2 - Dynamically interleaving randomly generated test cases
[3] Functional verification is a major bottleneck in hardware design, with up to 70% of development time and resources typically spent on it, and dynamic verification via randomized test generation and simulation is the dominant industrial practice. US7627843B2 - Dynamically interleaving randomly generated test cases
[4] The technique is co-cited with Model-Based Test Generation For Processor Design Verification (Lichtenstein, Malka, Aharon, IAAI 1994) and Test Program Generation for Functional Verification of PowerPC Processors in IBM (Aharon et al., 32nd DAC, 1995) as test generators used in processor design verification. US7627843B2 - Dynamically interleaving randomly generated test cases
[5] The technique belongs to a 1990s lineage of constraint- and graph-based processor verification approaches including Symbolic Model Checking (McMillan, 1993), the SMV System (McMillan, 1992), Symbolic Instruction Graphs (Chandra et al., 1994), Constraint Solving for Test Case Generation (Chandra & Iyengar, 1992), Automatic Test Program Generation for Pipelined Processors (Iwashita et al., 1994), and Architecture Validation for Processors (Ho et al., 1995). A methodology for processor implementation verification | Springer Nature Link