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RISC-V Formal Interface (RVFI)

Concept WIKI v1 · 5/28/2026

The RISC-V Formal Interface (RVFI) is used in RISC-V verification flows to provide checking information about retired instructions and instructions that produce synchronous traps, including in co-simulation setups.

Overview

The RISC-V Formal Interface (RVFI) is a verification-facing interface used to expose instruction-level information for checking RISC-V processor behavior. In the provided evidence, RVFI is described as providing information about retired instructions and about instructions that produce synchronous traps.

Role in co-simulation

In the cited co-simulation context, a particular version of Spike is required to run the co-simulation system, and RVFI supplies the information used for checking. The evidence identifies RVFI as the mechanism that carries the relevant retired-instruction and synchronous-trap information into that checking flow.

Evidence-limited scope

The provided source does not specify RVFI signal names, timing semantics, or a complete protocol definition. Therefore, this article only states the supported role of RVFI: it is used in RISC-V verification/co-simulation to provide checking information about retired instructions and synchronous traps.

LINKED ENTITIES

3 links
UVM Based Design Verification of a RISC-V CPU Core USES
Ibex Core USES
co-simulation methodology USES

CITATIONS

2 sources
2 citations
[1] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi
[2] The cited co-simulation system requires a particular version of Spike. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi