RISC-V Formal Interface (RVFI)

Concept

The RISC-V Formal Interface (RVFI) is used in RISC-V verification flows to provide checking information about retired instructions and instructions that produce synchronous traps, including in co-simulation setups.

First seen 5/28/2026

Last seen 6/8/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

The RISC-V Formal Interface (RVFI) is a verification-facing interface used to expose instruction-level information for checking RISC-V processor behavior. In the provided evidence, RVFI is described as providing information about retired instructions and about instructions that produce synchronous traps.

Role in co-simulation

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

RVFI Agent ← uses 1e

The RVFI Agent uses the RISC-V Formal Interface to monitor processor behavior.

cv32e40p ← uses 1e

cv32e40p exposes RISC-V Formal Interface signals used by the RVFI Agent.

LINKED ENTITIES

3 links

UVM Based Design Verification of a RISC-V CPU Core USES Extracted graph relationship

Ibex Core USES Extracted graph relationship

co-simulation methodology USES Extracted graph relationship

CITATIONS

2 sources

2 citations — click to collapse

[1] RVFI is used to provide information about retired instructions and instructions that produce synchronous traps for checking. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi

[2] The cited co-simulation system requires a particular version of Spike. [PDF] UVM based design veri cation of a RISC-V CPU core - POLITesi