Overview

Coverage-guided Aging is a coverage-driven technique for cross-level processor verification based on endless randomized instruction stream generation. The approach uses functional coverage feedback to guide test generation over time rather than relying only on unconstrained randomized instruction streams.

In the described cross-level setup, separate random instruction generators are initialized with the same cryptographic seeds for each core, causing them to provide the same endless randomized instruction stream. The instruction-set simulator (ISS) first executes part of the stream, while the RTL processor later fetches its stream through a core adapter that accounts for micro-architectural effects such as pipelining, prefetching, and fetch buffering.

Role in the verification loop

Coverage-guided Aging is implemented around two main components:

• Coverage-Observer: monitors the ISS internal state, samples executed instructions, maps them to coverage points, measures functional coverage, performs coverage aging, and emits hints when functionality should be covered again.
• Instruction-Injector: consumes the observer's hints and injects instructions intended to cover the requested functionality.

The paper notes that functional coverage can, in principle, be specified with arbitrary complexity and is used to guide test generation over time. In the work described, coverage points are defined as the cross-product of instruction groups.

Context in cross-level processor verification

The wider verification flow compares an RTL core against an ISS. After execution, the core and ISS write results to separate memories, and a comparator checks for functional differences by comparing register-value changes while accounting for different timing behavior between the cores. Coverage-guided Aging supplies the coverage feedback loop that steers the otherwise endless randomized instruction stream.

Reported effect

The DATE 2022 paper reports that Coverage-guided Aging produced a more regular coverage distribution for randomized instruction streams. In the same evaluation context, the authors report finding an intricate microarchitecture-related bug in an already heavily tested industrial processor and its accompanying testbench infrastructure.