2026-06-02
1 items 49 entities 64 connections
Processed 49 entities and 64 relations.
functional verification code generation microprocessor RTL model pseudorandom code generation heuristic-based code generation self-checking code diagnostic program architectural simulator speculative execution cache coherency multiprocessor verification constraint solving instruction template Intermediate Code Representation register allocation Abstract Graph Description diagnostic database instruction histogram event coverage trace file simulation-based verification branch prediction pipeline bypass superscalar processor template placement algorithm user-assisted code generation post-processing trace analysis SBVer BRVer MPVer MPApplicationVerifier Theo Profiler Ans refdif streamer RTL simulator AVPGEN MTPG Code Generation and Analysis for the Functional Verification of Microprocessors Anoosh Hosseini Dimitrios Mavroidis Pavlos Konas Silicon Graphics Inc. SPLASH-2 benchmarks memory management unit external interface unit DVT team