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Dynamic Biased Pseudo-Random Test Program Generation

Technique

Dynamic Biased Pseudo-Random Test Program Generation is a functional verification technique, introduced for processor design verification, in which test programs are synthesized dynamically and with biases that steer instruction and operand selection toward corner cases and untested behavior. It was applied to verify the IBM RISC System/6000 and was subsequently referenced as part of broader methodologies for processor implementation verification.

First seen 8/1/2026
Last seen 8/1/2026
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Dynamic Biased Pseudo-Random Test Program Generation

Overview

Dynamic Biased Pseudo-Random Test Program Generation is a functional verification technique used in processor design verification. Rather than relying solely on hand-written tests, the approach generates test programs dynamically, while applying biases that skew the random selection of instructions, operands, and program constructs toward situations that are unlikely to be covered by uniform random testing.

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Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator ← uses 100% 1e
The paper presents verification of the IBM RISC System/6000 using dynamic biased pseudo-random test program generation.

LINKED ENTITIES

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Verification of the IBM RISC System/6000 by a Dynamic Biased Pseudo-Random Test Program Generator USES Extracted graph relationship
Test Program Generation for Functional Verification of PowerPC Processors in IBM EXTENDS The PowerPC test program generation work by IBM authors extends the dynamic biased pseudo-random generation approach to subsequent IBM processor families.
Model-Based Test Generation For Processor Design Verification EXTENDS Model-based generation by IBM authors generalizes biased pseudo-random generation with architectural models and coverage feedback.
AVPGEN — A Test Case Generator for Architecture Verification RELATED AVPGEN is a contemporaneous test-case generator for architecture verification that shares goals with dynamic biased pseudo-random generation.
Design Verification of the HP9000 Series 7000 PA-RISC Workstations RELATED HP's PA-RISC verification applied comparable generator-driven verification techniques to industrial processor design.
Analyzing Partition Testing Strategies RELATED Partition testing analysis provides theoretical grounding for biased selection from partitioned input domains used in this technique.
The Pentium Bug, an Industry Watershed CONTEXT The Pentium bug case illustrates the real-world cost of inadequate functional verification that motivates biased pseudo-random generation.

CITATIONS

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8 citations — click to expand
[1] Dynamic Biased Pseudo-Random Test Program Generation was introduced for verifying the IBM RISC System/6000, as described by Aharon et al. in the IBM Systems Journal, April 1991. A methodology for processor implementation verification
[2] The technique was subsequently extended to PowerPC processor verification at IBM. A methodology for processor implementation verification
[3] Model-based generation by IBM authors generalizes biased pseudo-random generation with architectural models. A methodology for processor implementation verification
[4] The Pentium floating-point bug highlighted the cost of inadequate functional verification, motivating biased generation. A methodology for processor implementation verification
[5] HP applied generator-driven techniques to PA-RISC workstation verification. A methodology for processor implementation verification
[6] AVPGEN provided a related architecture-verification test-case generator. A methodology for processor implementation verification
[7] Coverage-directed generation using symbolic techniques extended biasing with coverage feedback. A methodology for processor implementation verification
[8] Weyuker and Jeng's partition testing analysis provides theoretical grounding for biased selection. A methodology for processor implementation verification