Overview

A directed test is a targeted verification technique that uses explicitly prepared stimulus to exercise specific functionality. In the processor-verification flow described in the evidence, directed stimulus can be provided by loading a directed scenario from a file containing a pre-assembled program trace. This approach is useful for reusing directed tests produced by a processor software team and for covering specific processor functions.

Role in processor verification

Directed tests address cases where the verification intent is known in advance and the stimulus should follow a specific sequence. For processors, an example implementation is a scenario class that reads a pre-assembled program as a directed scenario.

Directed testing is not presented as a complete replacement for other stimulus methods. The evidence states that the time required to create traditional directed tests for complex microprocessors has become unreasonable because modern processors expose many corner cases, including complex instruction sets, pipeline behavior, execution strategies, instruction parallelism, scalar/vector operations, and fixed- and floating-point behavior.

Relationship to constrained-random and directed-random stimulus

The cited processor-verification methodology uses multiple scenario types:

• Constrained-random scenarios, which constrain randomly generated instruction streams toward useful classes of operations.
• Directed-random scenarios, which use controlled setup or data values, such as special memory patterns, while still allowing randomized instruction behavior.
• Directed scenarios, which are read from pre-assembled programs and used to target specific functionality.

A scenario generator can work with these scenario types by selecting and randomizing scenario objects until a user-specified stopping condition is reached. In this context, directed tests are one supported stimulus style within a broader verification strategy rather than the only stimulus source.

Typical use cases

Directed tests are appropriate when:

• A specific processor function must be covered.
• A known instruction trace or pre-assembled program already exists.
• Software-team tests can be leveraged as hardware verification stimulus.
• Random stimulus is unlikely to reliably produce the desired sequence or corner case.

Limitations

Traditional directed testing can become costly for complex processors because the number of important behaviors and corner cases is large. The cited source positions constrained-random verification as a way to overcome these limitations while still supporting directed and directed-random stimulus where they are useful.