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Custom Tracer for Execution Log Capture

Technique WIKI v1 · 6/8/2026

A verification technique that integrates a custom tracer directly into a RISC-V core (specifically the Hornet RV32IMF core) to capture execution logs during simulation. The captured logs are then automatically compared against a reference instruction set simulator (Spike) via structured CSV-based scripts, enabling the detection of subtle compliance and arithmetic errors.

Overview

A custom tracer for execution log capture is a verification technique in which a purpose-built tracing module is integrated into a processor core to record its runtime behavior during simulation. The captured execution logs are then post-processed and compared against a golden reference (such as the Spike ISS) to detect functional, architectural, and arithmetic compliance bugs that directed or constrained-random tests may miss.

In the context of the ISMSIT 2025 verification framework, the custom tracer is embedded inside the Hornet RV32IMF core. As the core executes test programs, the tracer produces structured execution log data that is automatically compared with Spike's reference output through CSV-based comparison scripts.

How It Works

  1. Integration – A custom tracer module is added to the DUT (the Hornet RV32IMF core) so that relevant architectural state, executed instructions, and arithmetic results are observable during simulation.
  2. Execution log capture – While RISCV-DV-generated random instruction sequences (and additional test cases) run on the core, the tracer records the relevant execution information.
  3. CSV-based structured output – The tracer's output is formatted as structured CSV files, making the logs amenable to automated script-based comparison.
  4. Automated comparison against Spike – Python-flow scripts compare the captured execution log against Spike ISS reference output, flagging mismatches as potential bugs.

Detected Error Classes

The technique has been shown effective at surfacing errors that directed testing typically misses, including:

  • Incorrect handling of IEEE-754 rounding modes in floating-point units.
  • Precision loss in arithmetic units such as division and square root.
  • Other subtle floating-point compliance deviations.

Role in the Verification Flow

The custom tracer serves as the observability bridge between the DUT and the reference model. Rather than relying solely on scoreboard signals, the tracer produces a complete, post-execution record that can be diffed against Spike. This makes it especially valuable for RISC-V cores with advanced arithmetic capabilities, where the IEEE-754 corner cases multiply quickly.

Tool and Flow Compatibility

Because the tracer produces plain structured (CSV) logs and the comparison is script-driven, the approach is compatible with both:

  • Open-source flows (Python-based scripts, Spike ISS).
  • Closed-source commercial flows (e.g., Xcelium).

Outcomes

Using this technique, the authors of the ISMSIT 2025 paper successfully uncovered and resolved multiple floating-point bugs in the Hornet RV32IMF core, while demonstrating compliance with both the RISC-V ISA specification and the IEEE-754 floating-point standard.

Related Entities

  • Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools — the ISMSIT 2025 paper that defines and applies this custom tracer technique as part of a broader reusable verification framework combining RISCV-DV with open and closed-source tools.
  • Hornet RV32IMF core — the RV32IMF RISC-V core into which the custom tracer is integrated; serves as the DUT that produces the execution logs.

LINKED ENTITIES

2 links
Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools USES
Hornet RV32IMF core USES

CITATIONS

5 sources
5 citations
[1] A custom tracer integrated into the Hornet RV32IMF core captures execution logs. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[2] Captured execution logs are automatically compared with Spike through structured CSV-based scripts. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[3] The approach detects subtle errors often missed by directed tests, including incorrect IEEE-754 rounding-mode handling and precision loss in division and square root. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[4] The framework successfully uncovered and resolved multiple floating-point bugs in the Hornet core and demonstrated compatibility with both open-source (Python flow, Spike ISS) and commercial (Xcelium) tools. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[5] The technique ensures compliance with RISC-V and IEEE-754 standards, providing a scalable, flexible foundation for verifying cores with advanced arithmetic capabilities. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)